from the golden response upon the execution of a test program, the fault coverage of the test program is 75%. As each single fault simulation is time-consuming, fault simulation of all the faulty processor models would consume an enormous amount of time. Also, the response collection of test programs, where every observable point must be recorded in each cycle, is computationally intensive.
1.7 Motivation and Objectives
programs would likely to have lesser test quality in terms of fault coverage. To deal with the challenges in the detection and recovery for the temporary faults, a fault-tolerant schedule with optimal test program size must be developed.
To summarize, the motivation for this thesis is “to develop a low-cost, high quality, and faster SBST process for modern processors with the help of improved performance in the execution of SBST code synthesis, optimization, and application phases.”
Now, we explain four major challenges in the SBST code synthesis, application, and optimization phases (Phases C, D, and E of the SBST procedure shown in Fig. 1.3).
1. Detection of Hard-to-test Faults and its Preservation
Genetic algorithm-based approaches are widely accepted methods to search for high-quality self-test programs for processors. But the overall coverage of these test solutions was insufficient because the corner cases, which are the hard-to-detect faults, were never taken care of. During the automatic test program generation, the intermediate test programs comprising instructions which detect the hard faults must be sustained to constitute a final test solution of improved coverage. Further, these approaches could not guarantee the test quality because the fault evaluation metrics, such as the statement coverage, were not well-correlated with the physical faults. Generally, gate-level fault models are closely correlated with physical faults.
So, we must adopt a high-level fault model which is closely correlated with the gate- level fault models and therefore, would be closely correlated with the real physical faults.
When sequences of instructions which could possibly detect the corner cases are se- lected, a higher preference must be assigned to them to help them survive through the future generations. As these sequences may never get reproduced, it is neces- sary to conserve these test programs, which could contribute to the final optimal solution with higher coverage. So, our objective is to enhance the GA-based self- test synthesis by preserving the instruction sequences which detect the hard-to- detect faults. Also, the adopted fault models must have a high correlation with the gate-level fault models. Otherwise, a test program that detects every fault mod- eled by the adopted fault model may not be able to detect sufficient real physical faults.
2. A Faster Test Program Synthesis
The overall test synthesis time consumed by the previousµGP approaches was in- considerably huge. Further, if the evolutionary module comprehensively searches for the hard-to-detect faults, the test synthesis would be further delayed. This could be avoided by reducing the number of costly external fault evaluations for redundant test programs. So, our objective is to accelerate the test synthesis pro- cedure along with the detection of hard-to-detect faults by reusing the existing test programs of identical characteristics. The test codes, developed using the evolu- tionary process, that produce similar fault simulation responses must be identified and reused for a faster fault evaluation.
3. Effective Test Program Compaction and Test Execution Time Reduc- tion
The automated SBST synthesis [2, 41] could be employed for developing either a monolithic test code for the whole processor circuit or a set of test codes for the processor modules. In both cases, the test code must have a huge number of se- lected instructions to sensitize all the testable processor functionalities. However, a larger SBST code leads to performance overhead due to higher test code down- load time [63], and a longer execution time escalates the test application time.
Also, in the online testing of safety-critical embedded processors, smaller test code execution is an extremely crucial requirement. So, test code optimization, in terms of execution time and size, has been crucial for the effectiveness of SBST testing of processors [64].
Some of the recent techniques in test code optimization [4, 65] have demonstrated redundant instruction elimination methods to maximize the test compaction. How- ever, the number of fault simulations required to identify the redundant instruc- tions of test code is proportional to the test code size. So, a huge number of fault simulations have to be conducted for the optimization of larger test code. As the number of fault simulation required for test compaction increases, the time con- sumed for test compaction, which is the overall computational cost, also increases.
Instruction restoration and instruction removal techniques [4, 65] guarantee the
1.7 Motivation and Objectives
elimination of redundant instructions in terms of coverage with a reasonable com- paction rate. But the computational cost (CC) is huge for these techniques since efficient test compaction needs large number of fault simulations. So, our objec- tive is to develop a test optimization technique with adequate compaction rate and reasonable computational cost.
4. Online Detection of Intermittent Faults
During the operational stage of the processor, many temporary faults occur due to extreme operating conditions. These faults, called intermittent faults, appear mo- mentarily, lasts for some time, and may turn into permanent faults. Generally, the intermittent faults are activated by processor wear out and excessive fluctuations in temperature and voltage. The fault detection latency is the time gap between the fault occurrence and its detection. If the fault detection latency is higher, the reliability, which is the probability that a system does not deteriorate during a specific time interval, would be lesser. A self-test task must provide an optimal fault detection latency to detect the intermittent faults and must be schedulable along with a set of periodic real-time tasks.
Larger SBST codes would detect most of the faults but reliability will be lesser due to high fault detection latency. If an intermittent fault occurs just after a large test period, fault detection latency will be higher, which may cause system errors. Smaller SBST self-test codes with smaller fault detection latency realize rapid detection and recovery of intermittent faults. As the intermittent faults occur irregularly at the same location, smaller self-test codes must be regularly executed with a short test period to efficiently trace them. But these minimal test programs could have less reliability due to low fault coverage.
To deal with this trade-off, optimal and reliable set of fragments must be discovered with significant self-test quality (coverage) and minimal fault detection latency. So, our objective is to design a high-reliability online fault detection model that could test low-cost, real-time embedded processors for the intermittent faults.