2.2 Advanced SBST Techniques
2.2.4 SBST Code Application
2.2 Advanced SBST Techniques
compaction would be very high. Instruction restoration and instruction removal tech- niques [4] guarantee the elimination of redundant instructions in terms of coverage with a reasonable compaction rate. Since efficient test compaction needs a large number of fault simulations and single fault simulation takes a significant amount of time, the overall computation cost of these test compaction techniques is large.
A low-cost, instruction-wise test optimization technique that yields adequate test compaction could be introduced by enhancing the existing A1xx technique [4]. In this possible modification, a high-level logic simulation could be used to replace the preceding blocks of a restoring block of instructions with a smaller set of instructions that yields similar fault coverage. Also, every group of independent instructions could be investigated to identify and remove the redundant groups which do not contribute towards the overall fault coverage.
Concurrent testing [96] detects the operational faults with the help of various methods for hardware redundancy, software redundancy, and time redundancy. In these meth- ods, additional instances of a normal application, which is also termed as mission task, concurrently execute using extra hardware, software, or time. Non-concurrent testing employs test patterns periodically between the task execution [97]. To reduce redun- dancy cost and power consumption of online testing,concurrent testing techniques were replaced with non-concurrent, periodic testing methods.
The test patterns must be executed in the processor frequency in order to trace the intermittent faults, which are instantaneous in nature. If not, some of them might go undetected. To carry out a dynamic at-speed processor testing [28], where the test pat- terns are applied in the actual operating speed of the processor, SBST methodologies have been proposed [16,31,32,34,54] and are widely applied in the online testing domain.
SBST approaches are non-intrusive as the circuit design does not require any modifi- cation for testing purpose. Besides, test execution has no hardware overhead which reduces the test cost and leads to zero chip area penalty [33]. For the above reasons, SBST methods are used for the detection of intermittent faults in online periodic testing.
The advances on online testing [97–100] discuss the periodic testing techniques with SBST programs being periodically executed to identify the faults in the processor com- ponents. Further, the recent progress in the fault-tolerance domain of the intermittent faults demonstrate efficient detection, diagnosis, and recovery approaches [95, 101].
A probabilistic cost function for SBST programs is introduced in [97] using the reliability analysis of intermittent faults in pipelined processors. This cost function helps in reducing the SBST execution cost during the online periodic testing. Also, this technique enhances the methodology proposed in [99] with the addition of advanced SBST programs for the pipeline and exception logic components to increase the fault coverage up to 96.67%.
Xenoulis et al. [100] proposes an SBST program development scheme for processors with single and double-precision floating point units. The test pattern generation (TPG) schemes for floating point units are selected corresponding to the target requirements [64]
to develop low-cost self-test programs. However, the above cost-prohibitive self-test generation schemes [97, 99, 100] could not guarantee efficient test program utilization and schedulability.
2.2 Advanced SBST Techniques
D. Gizopoulos [98] has formulated a method for the effective utilization of self-test codes for the online periodic testing of medium cost, real-time embedded processors.
With the help of rate-monotonic scheduling (RMS) mechanism, this technique could achieve an improved self-test utilization or self-test quality in addition to the schedula- bility realized for the real-time mission tasks. However, D. Gizopoulos [98] have focused on the enhancement of the self-test quality disregarding the instruction set characteris- tics of the self-test programs. Also, the schedulability of self-test programs and a larger set of mission tasks on multi-core processors would necessitate advanced scheduling ap- proaches.
A Stochastic Activity Networks (SAN)-based recovery, proposed in [95], deals with the fault tolerance of multicore processors against intermittent faults. Based on the failure rate and the defective processor location, SAN devises a recovery action for the performance enhancement of an intermittent fault-sensitive processor.
Rashid et al. [101] evaluate the impact of intermittent faults on processors using a SPEC2006 benchmark and Alpha Sim, which is a microarchitectural fault injection tool.
In their work, they injected 3000 faults to the considered microarchitectural components and subsequently observed that the majority of the intermittent faults lead to system crash. In other words, 67% of the intermittent faults were non-benign and 79% of these non-benign faults caused a system crash (i.e., a hardware trap). The goal of their work was to study the effectiveness of software-based techniques in the intermittent fault diagnosis and recovery. Although the software-based technique takes away the performance overhead of a separate test process, huge memory overhead is incurred as the processor state is to be logged continuously.
As the intermittent faults could occur irregularly at the same location, the self-test codes must be regularly executed with a short test period to efficiently trace them. D.
Gizopoulos [98] suggested that the self-test quality could be improved when the self-test tasks are executed with larger execution time and enhanced self-test utilization. But the proposed techniques in [98] will increase the self-test period to achieve maximum utilization. If the self-test period is increased, fault detection latency also would increase, and subsequently, some of the instantaneous intermittent faults may be left undetected.
If an intermittent fault occurs just after a large test period, fault detection latency will be higher, which may cause system errors. The tradeoff between test utilization and
fault detection latency in [98] could be dealt only if efficient, small chunks of SBST codes are executed frequently between the mission tasks, i.e., smaller, coverage-efficient test programs are intermittently executed during a self-test period to reduce the fault detection latency.
Shorter, reliable SBST test code fragments must be discovered and executed inter- mittently in a self-test period to immediately detect the intermittent faults with minimal fault detection latency. But smaller test codes might have lesser fault coverage, which could leave some of the intermittent faults undetected. So, the test fragment synthesis must consider both fault detection latency and test quality (fault coverage) in devel- oping reliable fragments to be applied in appropriate execution windows between the execution of the mission tasks.
The tradeoff between test quality and fault detection latency could be improved using the application of test program fragments with high reliability. Test programs with smaller execution time and adequate fault coverage could be selected in order to detect the intermittent faults. These test codes must be identified with the help of reliability evaluations to get executed periodically during the operational stage of the processor with shorter time periods.