Implementation of Multioperand Redundant Adders on FPGA

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International Journal of Electrical, Electronics and Computer Systems (IJEECS)

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ISSN (Online): 2347-2820, Volume -3, Issue-2 2015 9

Implementation of Multioperand Redundant Adders on FPGA

1Aswathy S V, ²Senthil Murugan

1,2ECE Department, Amrita School of Engineering, Kollam.

Abstract — The use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on FPGAS due to their fast carry-chain resources as well as the area overhead of the redundant adders when they are implemented on FPGAs. This project presents the efficient implementation of redundant adders on FPGA through generic carry save compressor trees, by using fast carry resources. Its advantage is that it reduces the addition time by limiting the length of carry propagation chains.

I. INTRODUCTION

FPGA structure contains matrix of logic elements (LEs) by interconnection of resources. Each LE consist of several n-input lookup tables and flip-flops .But in modern FPGA LEs consist of multipliers, SRAM and admit parallel computing[2].

There are many cases need to add more than two numbers together, this is called multioperand addition.

Parallel multioperand addition is implemented in [1], used generalized parallel counters have reduced delay and increase in area and not valid I n 4-LUT based FPGAs.

II . MULTIOPERAND ADDITION USING

CS COMPRESSOR TREES ON FPGA

Multioperand addition used in filters, multiplication, digital signal processing and others. To achieve this redundant adders are used. Due to the efficient implementations of CPAs, the use of redundant adders has usually been rejected in FPGA technology. The latest studies have demonstrated that redundant adders can be effectively mapped on FPGA structures reducing area overhead and improving speed. Most usual representation of this by carry- save adders (CSA). The straightway of adding m numbers (all n bits wide) is to add the first two, then add that sum to the next, and so on. This requires a total of m − 1 additions, for a total

gate delay of O(mlg n) .Using carry save addition, the delay can be reduced . The idea is to take 3 numbers that we want to add together, x + y + z, and convert it into 2 numbers c + s such that x + y + z = c + s, and do this in O(1) time. The reason why addition cannot be performed in O(1) time is because the carry information must be propagated. In carry save addition, we restrict from directly passing on the carry information until the very last step. A CS adder adds three numbers using an array of full adders without propagating the carries. In this case the full adder is usually known as 3:2 counter.

The result is a CS number which is composed of a sum word and a carry word.

Fig.1. A Full Adder is equal to a Carry Save Adder block [3]

III. HIGH LEVEL IMPLEMENTATION

To efficiently map multioperand carry save compressor trees on FPGAs, Fig.2a, shows an example of the linear array structure for a 5:2compressor tree. At a low level design, the circuit could be implemented by connecting FAs shown in Fig.2b.Fig.2c shows the implementation of this by means of standard CPA instantiation, has the following advantages [2].

 Utilization of the specialized carry logic.

 Portability between different FPGA families.

 Easy to design a parametrizable compressor tree.

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International Journal of Electrical, Electronics and Computer Systems (IJEECS)

________________________________________________________________________________________________

ISSN (Online): 2347-2820, Volume -3, Issue-2 2015 10

Fig.2. 5:2 linear array compressor tree into CPA array[2]

IV. RESULTS AND COMPARISON.

Fig.3. one bit CSA as 3:2 counter

Fig.4.Fourbit as 5:2CSA linear array.

Fig.5. 5:2CSA into standard CPA Table 1.Comparison of Device Utilization

Logic Utilization

Used in5:2CS

A

used in 5:2CSA

into standard

CPA

availab le

Number of 4 input LUTs

26 23 1536

Number of occupied Slices

15 13 768

Number of Slices containing only related logic

15 13

Number of slices containing unrelated logic

0 0

Total number of 4 input LUTs

26 23 1536

Number of bonded IOBs

51 32 124

Average Fan out of Non Clock Nets

2.35 1.95

IV.CONCLUSION.

Efficiently implemented different carry save compressor trees on FPGA. The high level implementation of carry save compressor trees based on CPAs have ease of use to make it parametrizable ,portability between different FPGAs and it uses the specialized carry logic.

They used less area and high speed than regular compressor trees .

REFERENCES

[1]. H. Parandeh-Afshar, P. Brisk, and P. Ienne,

“Efficient Synthesis of Compressor Trees on FPGAs,” Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), pp. 138-143, 2008 [2]. Javier Hormigo, Julio Villalba, Member, IEEE, and Emilio L. Zapata, “Multioperand Redundant Adders on FPGAs”IEEE Transactions On Computers,vol.62,no.10,pp.2013-2025,Oct.2013 [3]. Loh “Carry Save Addition” CSB3220,Processor

Design,Spring 2005,Feb 2005

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