Copyright
IIT Kharagpur
List of Figures
1.1 Flow of a typical analog high-level design procedure . . . 2
2.1 Optimization-based design flow . . . 17
2.2 Simulink based behavioral model . . . 21
3.1 2D projection of a four dimensional sample space. . . 36
3.2 Non-linear relation between the sample space and the input, output space. . . 37
3.3 An outline of the procedure for generation of training data. . . 38
3.4 Outline of GA-based hyperparameter selection procedure . . . 44
3.5 Topology sizing methodology using GA optimizer with LS-SVM model 48 3.6 PMOS OTA circuit . . . 49
3.7 Scatter Plot of the constructed models. . . 52
3.8 Considered system for Experiment 3. . . 54
3.9 Noise as function of Gm1 and Gm2 . . . 58
3.10 Power as function of Gm1 and Gm2 . . . 58
3.11 Input parasitics as function of Gm1 . . . 59
4.1 Top-down generation of an optimal topology for linear analog systems 65 4.2 Block diagram of a CT ΣΔ modulator . . . 67
4.3 Functional topology of a 4th order CT ΣΔ modulator. . . 69
4.4 Functional topology for a general nth order CT ΣΔ modulator . . . . 70
4.5 A generic 3rd order CT modulator with GmC loop-filter. (Gaij ≡ Gmaij) . . . 71
4.6 SNR plot for two topologies generated through topology transforma- tion, establishing the invariant property. . . 75
Copyright
IIT Kharagpur
vi LIST OF FIGURES
4.7 Complete flow of the topology generation process for ΣΔ modulator
system. . . 84
4.8 The generated 3rd order modulator topology. . . 88
4.9 Characterization of the generated 3rd order modulator topology. . . . 90
4.10 Chosen standard topologies of a 3rd order modulator for comparison. 91 4.11 SNR/DR comparison between the generated, CIFF and DF topology. 92 4.12 Monte Carlo analysis plot for sensitivity comparison between the gen- erated (optimized), CIFF and DF topology . . . 93
4.13 The generated 4th order modulator topology and the corresponding SNR plot. . . 97
4.14 The CIFF 4th order topology. . . 98
4.15 Bar diagram of peak SNR deviation for 5% coefficient variation for the generated (optimized) and the CIFF 4th order modulator topology. 99 5.1 Meet-in-the-middle way of constructing D, D = Da ∩Dc, S is the search space. . . 107
5.2 Feasible design space and its subspaces. . . 109
5.3 DSE mechanism. . . 110
5.4 Considered system for experimentation. . . 114
5.5 SPICE output amplitude with 3 mV input . . . 117
5.6 3rd order OTA-C based ΣΔ modulator topology . . . 119
5.7 Comparator circuit . . . 120
5.8 Behavioral and SPICE simulated SNR plot of the modulator. . . 121
Copyright
IIT Kharagpur
List of Tables
3.1 Transistor Sizes and Feasibility Constraints for OTA . . . 49
3.2 Grid search technique using hold out method . . . 50
3.3 Grid search technique using 5-fold cross validation method . . . 50
3.4 GA technique using hold out method . . . 51
3.5 GA technique using 5-fold cross validation . . . 51
3.6 Comparison between GA and Grid search technique for LS-SVM con- struction . . . 51
3.7 Construction of Nonlinear Performance Model . . . 53
3.8 Comparison between our methodology and EsteMate . . . 53
3.9 Functional Specs and Design constraints . . . 55
3.10 Transistor Sizes and Feasibility Constraints for Preamplifier . . . 56
3.11 Accuracy of Preamplifier block . . . 56
3.12 Synthesized Topology Parameters . . . 60
3.13 Comparison of Predicted performances and SPICE value . . . 60
4.1 Non-idealities of the OTA-C component blocks . . . 74
4.2 Non-idealities considered . . . 89
4.3 Comparision of behavior under ideal and non-ideal conditions . . . . 89
4.4 Comparison in terms of yield for coefficient variation . . . 92
4.5 Comparison between the topologies for relative power and complexity 95 4.6 Comparision of behavior under ideal and non-ideal conditions: 4th order modulator . . . 96
4.7 Comparison in terms of yield for coefficient variation: 4th order mod- ulator . . . 96
4.8 Comparison between the topologies for relative power and complexity 98 5.1 Application bounded constraints: Experiment 1 . . . 115
Copyright
IIT Kharagpur
viii LIST OF TABLES
5.2 Circuit Realizable Constraints: PA block . . . 115
5.3 SVM Performances: Experiment 1 . . . 116
5.4 Translated Specifications: Experiment 1 . . . 116
5.5 GA results: averaged over 10 runs, 3.0 GHz 512 MB RAM PIV PC . 116 5.6 End results: Experiment 1 and 2 . . . 117
5.7 Application bounded constraints: Experiment 2 . . . 118
5.8 SVM Performances: Experiment 2 . . . 118
5.9 Translated Specifications: Experiment 2 . . . 118
5.10 Feasibility constraints for OTA and Comparator: Experiment 3 . . . 120
5.11 Translated Specifications: Experiment 3 . . . 121
5.12 End results: Experiment 3 . . . 122
Copyright
IIT Kharagpur
Abbreviations and Symbols
ADC Analog-to-Digital Converter
AMS Analog Mixed Signal
ANN Artificial Neural Network
C Capacitor
CIFF Cascaded Integrator Feed Forward
CMOS Complimentary Metal Oxide Semiconductor
DF Distributed Feedback
DR Dynamic Range
DSE Design Space Exploration
GA Genetic Algorithm
IC Integrated Circuit
LS-SVM Least Squares Support Vector Machine
MEMS Micro Electromechanical Systems
NTF Noise Transfer Ratio
OTA Operational Transconductance Amplifier
PLL Phase Locked Loop
RBF Radial Basis Function
RF Radio Frequency
SA Simulated Annealing
SFG Signal Flow Graph
SNR Signal-to-Noise Ratio
SPICE Simulator Program with Integrated Circuit Em- phasis
SRM Structural Risk Minimization
STF Signal Transfer Ratio
SVM Support Vector Machine
B Parameterized behavioral models
Copyright
IIT Kharagpur
x ABBREVIATIONS AND SYMBOLS
X¯ Set/vector of design variables/parameters
ρ¯ Set/vector of performance parameters
P Performance model
ΣΔ Sigma Delta
Dα Circuit-level design space
Dg Design space
Da Application-bounded specification space
Dc Circuit-realizable specification space
γ Regularization parameter
σ2 RBF kernel parameter
ARE Average relative error
R Correlation Coefficient
Gm OTA transconductance value
CL Load Capacitance
L(s) Transfer function in s domain (A,B,C,D) State space matrix tuple
T Component-level topology
TF Functional topology
SL12 L12 norm of the sensitivity function
W Observability Gramian matrix
K Controllability Gramian matrix
T Topology transformation operator
