A Novel Architecture of SRAM Cell for Low-Power Application

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ISSN (Print): 2278-8948, Volume-2, Issue-4, 2013

109

A Novel Architecture of SRAM Cell for Low-Power Application

Sunil Kumar Ojha & P.R. Vaya Department of E.C.E, Amrita School of Engineering Kasavanahalli, Carmelaram, P.O.Bangalore (INDIA) - 560 035

E-mail : [email protected], [email protected]

Abstract: Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction.

Many circuit techniques for active and standby power reduction in static and dynamic RAMS have been devised.

This paper presents a new static random access memory (SRAM) cell. The proposed SRAM cell uses two trapezoidal-wave pulses and resembles behavior of static CMOS 4T-SRAM. The elementary cell structure of proposed SRAM cell consists of two high load resistors which are constructed of PMOS, and NMOS switch which is necessary to restrict short circuit current. From the simulation results, we show that the energy consumption of the proposed circuit is lower than that of conventional SRAM cell.

Keywords- Conventional SRAM cell design, Proposed SRAM cell design, Simulation analysis

I. INTRODUCTION

Present day workstations, low-power processors, computers and super computers are using fast SRAMs and will require, in the future, larger density memories with faster access time. High-density, low-power SRAMs are needed for applications such as hand-held terminals, laptops, notebooks and IC memory cards, due to the fact that these devices frequently use battery as power source and hence it should consume power as low as possible, also it is necessary for maintaining low cooling and packing costs for these devices. The power dissipation reduction in SRAMs is not only due to power supply voltage reduction, but also due to low- power circuit techniques. An SRAM cell must be designed such that it provides a non-destructive read operation and a reliable write operation. These two requirements impose contradicting requirements on SRAM cell transistor sizing. In this paper we implemented a novel SRAM cell for low-power applications.

II. CONVENTIONAL SRAM CELL DESIGN An SRAM cell is the key SRAM component storing binary information. A typical SRAM cell uses two cross-coupled inverters forming a latch and access transistors. Access transistors enable access to the cell during read and write operations and provide cell isolation during the not-accessed state. An SRAM cell is designed to provide non-destructive read access, write capability and data storage (or data retention) for as long as cell is powered. We will discuss design and analysis of two different SRAM cells: a six-transistor (6T) CMOS SRAM cell and a SRAM cell with transmission gates. We will compare them with respect to power. In general, the cell design must strike a balance between cell area, robustness, speed, leakage and yield. Power reduction is one of the most important design objectives.

However, the power cannot be reduced indefinitely without compromising the other parameters. For instance, low-power can compromise the cell area also speed of operation. The mainstream six-transistor (6T) CMOS SRAM cell is shown in Figure -1, four transistors (Q1−Q4) comprise cross-coupled CMOS inverters and two NMOS transistors Q5 and Q6 provide read and write access to the cell. A 6T CMOS SRAM cell is the most popular SRAM cell due to its superior robustness, low power and low-voltage operation.

Figure -1 Conventional CMOS SRAM Cell.

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International Journal of Advanced Electrical and Electronics Engineering, (IJAEEE)

110 A. Read Operation

Prior to initiating a read operation, the bit lines are precharged to VDD. The read operation is initiated by enabling the word line (WL) and connecting the precharged bit lines, BL and BLB, to the internal nodes of the cell. Upon read access shown in Figure -2, the bit line voltage VBL remains at the precharge level. The complementary bit line voltage VBLB is discharged through transistors Q1 and Q5 connected in series.

Effectively, transistors Q1 and Q5 form a voltage divider whose output is now no longer at zero volt and is connected to the input of inverter Q2−Q4 (Figure -1).

Sizing of Q1 and Q5 should ensure that inverter Q2−Q4 do not switch causing a destructive read.

Figure -2 Read Operation of SRAM Cell.

B. Write Operation

During write operation one of the bit lines, BL in Figure -3, is driven from precharged value (VDD) to the ground potential by a write driver through transistor Q6.

If transistors Q4 and Q6 are properly sized, then the cell is flipped and its data is effectively overwritten. A statistical measure of SRAM cell writeability is defined as write margin. Write margin is defined as the minimum bit line voltage required to flip the state of an SRAM cell. The write margin value and variation is a function of the cell design, SRAM array size and process variation. A cell is considered not writeable if the worst-case write margin becomes lower than the ground potential. Note that the write operation is applied to the node storing a “1”. This is necessitated by the non-destructive read constraint that ensures that a “0”

node does not exceed the switching threshold of inverter Q2−Q4. The function of the pull-up transistors is only to maintain the high level on the “1” storage node and prevent its discharge by the off-state leakage current of the driver transistor during data retention and to provide the low-to-high transition during overwriting.

Figure -3 Write Operation of SRAM Cell.

C. Input & Output Waveform of Conventional 6T SRAM Cell

Given below screenshot -1: Shows the input word-line voltage (WL).

Given below screenshot -2: Shows the input bit-line voltages BL & BLB.

Given below screenshot-3: Shows the output voltages Q and QB.

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111 Given below screenshot - 4: Shows the power dissipation of the cell.

III. PROPOSED SRAM CELL DESIGN The proposed SRAM cell is shown in Figure - 4, it consists of two transmission gates in place of pass (access) transistors as shown in Figure -1, this is due to the fact that the transmission gates have low voltage drop compare to pass transistors, also in the given cell we have an additional NMOS which acts as a switch and also it is necessary to restrict a short circuit current when the data is written in the elementary cell.

However, the read and write operations of given circuit is same as that of conventional 6T CMOS SRAM cell.

Figure -4 Proposed SRAM Cell.

A. Input & Output Waveform of Proposed SRAM Cell Given below screenshot -1: Shows the input word- line voltage WL & WLB.

Given below screenshot -2: Shows the input bit-line voltages BL & BLB.

Given below screenshot-3: Shows the output voltages Q and QB.

Given below screenshot - 4: Shows the power dissipation of the cell.

IV. SIMULATION ANALYSIS

The conventional SRAM cell and the proposed SRAM cell are simulated by HSPICE simulator using a 90nm standard CMOS process technology. The

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112 parameters of the circuit and simulation conditions are summarized in Table - I.

Table-I

Device Name MOS Size (nm) PMOS (Q3 & Q4) W/L = 800/100 Other than those W/L = 400/100 Simulation Condition

Vdd 1.2v (DC)

WL 1.2v @ Trapezoidal

BL 1.2v @ Trapezoidal

A. RESULTS

We have simulated both the circuits conventional SRAM cell as well as proposed SRAM cell as per the parameters shown in Table-I and through simulation results we have shown that the power consumption of proposed SRAM cell is much less than that of conventional SRAM cell, also the Table-II shown below is the comparison of power dissipation of both the circuits.

Table –II

Conventional SRAM cell Proposed SRAM cell Pmax ≈ 60µw Pmax ≈ 16µw Pmin ≈ 40µw Pmin ≈ 3.5µw

V. CONCLUSION

In this paper, we have design and implemented a novel SRAM cell. We have also analyzed the power consumption of conventional SRAM cell as well as proposed SRAM cell. The proposed SRAM cell has used two trapezoidal-wave pulses for controlled switching current flow. We found that it is possible to reduce the power consumption of CMOS SRAM cell by adding transmission gates as well as an NMOS switch to conventional CMOS 6T SRAM cell.

VI. REFERENCES

[1] W.C. Athes , L.J. Svensson , J.G Koller , N.

Tzartzains , and E.Y-C. Chou, “Low-power Digital systems based on adiabatic- switching principles”, IEEE trans. VLSI Syst. Vol.2 no.4, pp. 398-407, Dec. 1994.

[2] Masood Qazi, Mahmut E. Sinangil, and Anantha P. Chandrakasan, “Challenges and Directions for Low-Voltage SRAM”, Copublished by the IEEE CS and the IEEE CASS 0740-7475/11/$26.00 2011.

[3] Kaushik Roy, Sharat C. Prasad, “Low-Power CMOS VLSI Design”, a John Wiley & Sons, 02- Feb-2009.

[4] Jan M. Rabaey, Anantha P.

Chandrakasan, Borivoje Nikolic, “Digital integrated circuits: a design perspective”, Pearson Education, 2003.

[5] Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, Tata McGraw-Hill Education.

[6] Neil H. E. Weste, David Money Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley, 2011.

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