Analysis of 128 Rows and single column SRAM in 90nm CMOS Technology

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International Journal of Electrical, Electronics and Computer Systems (IJEECS)

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ISSN (Online): 2347-2820, Volume -3, Issue-9 2015 49

Analysis of 128 Rows and single column SRAM in 90nm CMOS Technology

1Neha Sant, ²Apurva Gaikwad, ³P.P. Tasgaonkar

1,2,3Dept. of Electronics and Telecommunication Engineering College of Engineering, Pune-411005 Maharashtra, India Email : ¹[email protected], ²[email protected]

Abstract- A SRAM cell must meet requirements for operation in submicron/Nano ranges. The scaling of CMOS technology has significant impact on SRAM cell random fluctuation of electrical characteristics and substantial leakage current. In this paper we present simulation of single column with 128 rows with 6T SRAM cell and single 6T SRAM cell . To verify proper reading and writing of single column it will be simulated using cadence virtuoso tool in 90nm CMOS and analysed at 25°C with VDD of 1.2V.

Index Terms— SRAM Cell, SRAM Array, static noise margin, static power, dynamic power.

I. INTRODUCTION

Memory is an essential part of computer and microprocessor based system design. It is used to store data or information in terms of binary number (0 or 1).

Also data that is used in program as well as for executing the program are stored in the memory. Any digital system will require memory to store data. Generally memories are of two types (1) RAM and (2) ROM.

ROM is also called as read only memory as it is designed once and can be used for read purpose only.

While RAM called ad random access memory is used for both reading and writing. As CMOS technologies continue to scale down to deep Submicrometre levels, devices are becoming smaller and smaller and more sensitive to noise sources. Systems-on-a-Chip (SoCs) and other integrated circuits today are composed of nanoscale devices that are crammed in small areas. This causes supply lines and other signal sources in the circuit to largely affect the operations of the system. One example of such system where noise effects are of great concern is the SRAM because it is made up of large number of minimum sized devices which are sensitive to noise. The ever increasing need for high performance VLSI chips demands higher on-die SRAM requirements.

As a consequence, efficient SRAM scaling assumes importance in today’s VLSI design applications

One of the major issues in the design of an SRAM cell is stability. The cell stability determines the sensitivity of the memory to process tolerances and operating

conditions. It must maintain correct operation in the presence of noise signals. The stability of SRAM cell in the presence of DC noise is measured by the static noise margin (SNM). SNM is the amount of voltage noise required at the output nodes to flip the state of the cell.

This can be obtained using the voltage transfer characteristic (VTC) of the two cross coupled inverters of the SRAM cell.

The goal of this paper is to calculate static noise margin of 6T SRAM cell and simulation of 128 rows single column SRAM in 90nm technology for reading and writing

II. STATIC NOISE MARGIN OF 6T SRAM CELL

This section discusses the present methods used in obtaining the SNM of the SRAM cell.The structure of a 6 transistor SRAM cell, storing one bit of information, can be seen in Figure 1. The core of the cell is formed by two CMOS inverters, where the output potential of each inverter is fed as input into the other. This feedback loop stabilizes the inverters to their respective state.

Figure 1: Schematic of 6T SRAM cell

The access transistors and the word and bit lines, WL and BL, are used to read and write from or to the cell. In standby mode the word line is low, turning the access

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transistors off. In this state the inverters are in complementary state. When the pchannel MOSFET of the left inverter is turned on, the potential is high and the p-channel MOSFET of inverter two is turned off is low. To write information the data is imposed on the bit line and the inverse data on the inverse bit line . Then the access transistors are turned on by setting the word line to high. As the driver of the bit lines is much stronger it can assert the inverter transistors. As soon as the information is stored in the inverters, the access transistors can be turned off and the information in the inverter is preserved.

In above figure the width of the PMOS transistor is taken as 0.1um and width of NMOS transistor is taken as 0.25um This is chosen for better results of 6T SRAM cell.

III. THE PRE CHARGE CIRCUIT

The function of a pre charge circuit is to pre charge both the bit lines high. The function of SRAM is to charge the bit and bit bar lines to Vdd=1.2v.The pre charge circuit enables the bit lines to be charged high at all times except during read and write operation.

Figure 2: Schematic of Pre Charge circuit

IV. WRITE DRIVER CIRCUIT

The function of the SRAM write driver is to quickly discharge one of the bit lines from the pre charge level to below the write margin of the SRAM cell. Normally, the write driver is enabled by the Write Enable (WE) signal and drives the bit line using full-swing discharge from the pre charge level to ground.

Write driver uses four PMOS transistors and four NMOS transistors and input is given from Din to one of the PMOS and its inverted signal is given to another PMOS. When enabled by EN and ENB data that is either strong 0 or 1 may be applied by discharging BL or BLB from pre charge to ground level.

Figure 3: Schematic of Write driver circuit

V. SENSE AMPLIFIER

Sense amplifiers (SA) are an important component in memory design. The choice and design of a SA defines the robustness of bit line sensing, impacting the read speed.

Figure 4: Schematic of Sense Amplifier

Figure 5: sense amplifier

Figure 5 shows a schematic of our Current mode sense amplifier. The source nodes of transistors N6 and N7

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and output node of the inverters are connected to the output and body nodes of the pre-charge transistors, respectively. The SAEB, which is an inverted signal of SAE, is applied to the input nodes of the inverters.

When this amplifier is in sensing mode, SAE and SAEB are high and low, respectively. At this time, both the output voltages of the inverters become high. Because the body nodes are kept at VDD, the CMOS inverters do not affect pre-charge transistors P3 and P4.

VI. ROW DECODER

The below figure shows the schematic of simple and gate based decoder. The function of decoder is to select a particular word line depending on the inputs A and B.

The below is 7:128 decoder. The simple and gate based decoder is used. The 7:128 row decoder has 7 inputs, A, B, C, D, E, F, G and 128 outputs namely 1 to 128. The outputs of decoder act as a word line to each row. If the input sequence is 000000, the 0th word line will be selected. If the input sequence is 1111111, the 127th word line will be selected. This 7:128 decoder is implemented using one 3:8 decoder and eight 4:16 decoders. 3:8 decoder is implemented using inverters and NAND gates and 4:16 decoder is implemented using two 3:8 decoders

Figure 6: Schematic of 7:128 decoder

Figure 7: Schematic of 128 rows and single column The above schematic consists of a row decoder which has 7 inputs and 128 outputs these 128 outputs are connected to the word line of all 128 SRAMs.

The bit lines and bit line bar are connected to the bit lines of sense amplifier and pre charge circuit and write driver circuit for proper reading and writing of the data.

Here 63rd SRAM cell is selected for simulation with the help of row decoder and in this cell the data is written with the help of write driver circuit and it is read using sense amplifier.

VII. SIMULATION RESULTS

This Section clearly discuss about the simulation results of SRAM column, 6T SRAM cell, sense amplifier, 7:128 decoder. The work is carried out on cadence virtuoso the simulation is done using spectre.

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Figure 7: simulation of SRAM column

In this simulation zero was first written into 63rd SRAM cell which was selected using row decoder and this zero was read using sense amplifier as shown in figure above and can be seen that vout is 1.2 volts as sense amplifier has sensed the data.

Figure 8: Static noise margin of 6T SRAM cell Figure 8 shows simulation for static noise margin of 6T SRAM cell

Figure 9: Transient simulation of sense amplifier

Figure 10: Transient simulation for 7:128 decoder Figure 10 shows transient simulation for 7:128 decoder.

Here random inputs were given to the decoder and for that input transient simulation was done.

Static noise margin was found to be 377mvolts.

Performance summary of sense amplifier TABLE I Sensing

delay

Dynamic power

Static power Sense

amplifier

28.7ps 787.2nW 5.3nW

All these results were calculated using cadence virtuoso tool.

VIII. CONCLUSION

The schematic is designed for proper reading and writing of SRAM cell. The complete array which includes peripheral components such as memory bit cell, write driver circuit, pre-charge circuit, Sense amplifier are designed and integrated. The integrated SRAM Memory is capable of storing 1 bit in each cell of SRAM. The proposed work is operated with analog input voltage of 0 to 1.2v. The static noise margin for SRAM cell is found to be 377mVolts. The SRAM is designed and implemented in standard 90nm technology using Cadence virtuoso tool for schematic.

REFERENCES

[1] “Digital Integrated Circuits” Jan Rabaey

[2] Ili Shairah Abdul Halim, Noh Hud Basemu, Siti Lailatul Mohd Hassen, “Comparative Study on CMOS SRAM Sense Ampifiers using 90nm Technology”, 2013 International Conference on Technology, Jun 23-26, 2013.

[3] K. Dhanumjaya1, M. Sudha2, Dr.MN.Giri Prasad3, Dr.K.Padmaraju “CELL STABILITY

ANALYSIS OF CONVENTIONAL 6T

DYNAMIC 8T SRAM CELL IN 45NM TECHNOLOGY” Vol.3, No.2, April 2012 [4] Christiensen D.C. Arandilla, Anastacia B.

Alvarez, and Christian Raymund K. Roque

“Static Noise Margin of 6T SRAM Cell in 90-nm CMOS”

[5] Debasis Mukharji, Hemant Kr. Mondal, B. V. R.

Reddi, “Static Noise Margin Analysis of SRAM Cell for High Speed Operation”, IJCSI, Vol. 7, Issue 5, September 2010.

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