Analysis and Derivation of Clocked Sequential Circuits with State Graphs and Tables: A Sequential Parity Check, Analysis by Signal Trace and Timing Graphs - Status Tables and Graphs - General Models for Sequential Circuits, Sequence Detector Design, More Complex Design Problems, Guidelines for State Graph Construction, Serial Data Conversion, Alphanumeric state graph notation. Sequential circuit design: Design procedure for sequential circuits - design example, Code converter, Design of iterative circuits, Design of a comparator, Design of sequential circuits using ROMs and PLAs, Sequential circuit design using CPLDs, Sequential circuit design using FPGAs, Simulation and testing of sequential circuits, overview of computer aided design. Fault diagnosis in sequential circuits: circuit testing approach, transition control approach, state identification and fault detection experiment, machine identification, design of fault detection experiment.
Design of CMOS op-amps, compensation of op-amps, design of two-stage op-amps, power supply rejection ratio of two-stage op-amps, Cascode op-amps, measurement techniques of op-amps. Architecture of ARM Processors: Introduction to the Architecture, Programs Model-Operating States and Modes, Registers, Special Registers, Floating Point Registers, Behavior of the Application Program Status Register (APSR) - Integer Status Flag, Q Status Flag, GE Bits, Memory System-Memory System Functions, Memory Map , stack memory, memory protection unit (MPU), exceptions and interrupts-what are exceptions?, nested vectored interrupt controller (NVIC), vector table, error handling, system control block (SCB), debugging , Reset and reset sequence. Introduction to the arm instruction set: data processing instructions, branch instructions, load-store instructions, software interrupt instructions, program status register instructions, load constants, ARMv5E extensions, conditional execution.
Design of an N-bit register of serial-in-serial-out, serial-parallel-out, parallel-in 13.
TECH.- I YEAR- I SEMESTER
Since the current trend in computer architecture is towards chip multiprocessing, the architecture of multiprocessors with shared memory and chip-level interconnection (network-on-chip) will be covered as the future scope. Describe and explain instruction-level parallelism with static scheduling, out-of-order execution, and network-on-chip architectures. Principles and examples of instruction set - Introduction, classification of instruction set - memory addressing - type and size of operands, operations in the instruction set.
Pipelines: Introduction, basic RISC instruction set, Simple implementation of RISC instruction set, Classic five stage pipeline for RISC processor, Basic performance issues in pipelining, Pipeline dangers, Reducing pipeline branch penalty. Fault Tolerant Design: Basic Concepts - Static, Dynamic, Hybrid, Triple Modular Redundant (TMR) System, 5MR Reconfiguration Techniques, Data Redundancy, Time Redundancy and Software Redundancy Concepts. Self-checking circuits and fail-safe design: Basic concepts of self-checking circuits, Design of fully self-checking control, Checkers using m out of n codes, Berger code, Low cost residual code.
Fail Safe Design- Fault Safe Circuits, Fail Safe Design of Sequential Circuits Using Partition Theory and Berger Code, Fully Self-Controlled PLA Design. Design for Testability: Design for Testability for Combinational Circuits: Basic concepts of testability, controllability and observability, Reed Muller expansion technique, use of testable control and syndrome models. Integrated Logic Self-Test: BIST Basics- Memory Based BIST, BIST Effectiveness, BIST Types, Designing a BIST, Test Pattern Generation- Pulling TPGs, Exhaustive Counters, Ring Counters, Twisted Ring Counter, Linear Feedback Shift Register, Output Response Analysis-Commit ORAs, one person counter, transition counter, parity check, serial LFSRs, parallel signature analysis, BIST architectures-BIST related terminologies, A centralized and separate Board-level BIST architecture, Embedded Evaluation and Self-Test (BEST), Random Test Socket (RTS), LSSD on-chip self-test, Self.
Standard IEEE test access methods: Basic boundary scan, boundary scan architecture- Test access port, boundary scan registers, TAP controller, decoder unit, selection and other devices, boundary scan test instructions-mandatory instructions, board-level scan chain structure-A serial scan chain, multiple scan chain with one control test port, multiple scan chains with one TDI,TDO but multiple TMS, Multiple scan chain, multiple access port, RT Level limit scan insertion of limit scan test hardware for CUT, Two module test case, virtual limit scan tester, limit scan description language. Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology) – Jason Andrews – Newnes, BK and CDROM. System on Chip Verification – Methods and Techniques – Prakash Rashinkar, Peter Paterson and Leena Singh L, Kluwer Academic Publishers, 2001.
TECH.- I YEAR- II SEMESTER
Be able to explain real-time concepts such as preemptive multitasking, task priorities, priority inversions, mutual exclusion, context switching and synchronization, interrupt latency and response time, and semaphores. Able to work with real-time operating systems like RT Linux, Vx Works, MicroC /OS-II, Tiny OS. Real Time Operating Systems: Brief History of OS, Definition of RTOS, The Scheduler, Objects, Services, Characteristics of RTOS, Defining a Task, Query States and Scheduling, Task Operations, Structure, Synchronization, Communication and Concurrency.
Exceptions, Interrupts and Timers: Exceptions, Interrupts, Applications, Exception Handling and False Interrupts, Real Time Clocks, Programmable Timers, Interrupt Timer Service Routines (ISRs), Soft Timers, Operations. The student will learn the basics and advanced techniques in low energy design, a hot topic in today's power-driven market. Basics: Need for low power circuit design, sources of power dissipation - switching power dissipation, short circuit power dissipation, leakage power dissipation, power dissipation disorder, short channel effects - drain barrier lowering and punch through, surface scattering, velocity saturation , impact Ionization, effect of hot electrons.
Low power design approaches: Low power design using voltage scaling – VTCMOS circuits, MTCMOS circuits, architectural level approach – pipeline approaches and parallel processing. Low-voltage, low-power multipliers: introduction, overview of multiplication, types of multiplication architectures, Braun multiplier, Baugh-Wooley multiplier, Booth multiplier, introduction to the Wallace Tree multiplier. Low Power Low Power Memory: Basics of ROM, Low Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM, Memory Cell, Pre-Charging and Equalization Circuit, Low Power SRAM Technologies, Basics of DRAM, Self-Renewal Circuit, Future Trend and development of DRAM.
MAC Protocols: Introduction, Issues in Designing a MAC Protocol for Wireless Ad Hoc Networks, Design Goals of a MAC Protocol for Wireless Ad Hoc Networks, Classifications of MAC Protocols, Content Based Protocols, Content Based Protocols with Reservation Mechanisms , content-based MAC protocols with scheduling mechanisms, MAC protocols using directional antennas, other MAC protocols. Routing Protocols: Introduction, Issues in designing a routing protocol for ad-hoc wireless networks, classification of routing protocols, table-driven routing protocols, on-demand routing protocols, hybrid routing protocols, routing protocols with efficient flooding mechanisms, hierarchical routing protocols, power supply – Conscious Routing Protocols. Transport Layer Protocols: Introduction, Issues in Designing a Transport Layer Protocol for Wireless Ad Hoc Networks, Design Objectives of a Transport Layer Protocol for Wireless Ad Hoc Networks, Classification of Transport Layer Solutions, TCP over Wireless Ad Hoc Networks, Other Transport Layer Protocols for Ad Hoc Wireless Networks.
TECH.- II YEAR- I SEMESTER
Associative Memories & ART Neural Networks: Basic Concepts of Linear Associator, Basic Concepts of Dynamical Systems, Mathematical Foundation of Discrete Time Hopfield (HPF) Networks, Mathematical Foundation of Gradient Hopfield Networks, Transient Response of of continuous time, Applications of HPF in solving the optimization problem: Minimization of the tour length of traveling salesmen, Summarization of networks with digital output, Solving simultaneous linear equations, Bidirectional associative memory networks; Cluster structure, Vector quantization, Classical ART networks, Simplified ART architecture. Genetic Algorithms: Basic concepts of Genetic Algorithms (GA), biological background, generation of offspring, working principle, coding, fitness function, reproduction, inheritance operators, crossover, inversion and deletion, mutation operator, bitwise operators used in GA, Generative Cycle, Genetic Algorithm Convergence. Hybrid Systems: Types of Hybrid Systems, Neural Networks, Fuzzy Logic and Hybrid Genetic Algorithms, BPN Based Genetic Algorithms: GA Based Weight Determination, Fuzzy Back Propagation Networks: LR Type Fuzzy Numbers, Fuzzy Neuron, Fuzzy BP, Fuzzy BPN Architecture, Inference from fuzzy BPN.
Programmable DSP: Evaluation of programmable digital signal processors, DSP processors for mobile and wireless communications, multimedia signal processing processors. Understand the skills needed in writing a headline. Ensure good paper quality on first submission. Course objectives: Students will be able to learn to demonstrate a critical understanding of key concepts in disaster risk reduction and humanitarian response. critically evaluate the policy and practice of disaster risk reduction and humanitarian response from several perspectives. develop an understanding of humanitarian response standards and practical relevance in specific types of disasters and conflict situations. critically understand the strengths and weaknesses of disaster management approaches,. planning and programming in different countries, especially the home country or countries in which they work.
Nishith, Singh AK, “Disaster Management in India: Perspectives, Problems and Strategies” New Royal book Company. Engineering scholars equipped with Sanskrit will be able to explore the vast knowledge of ancient literature. To discuss the role of socialism in India after the onset of the Bolshevik Revolution in 1917 and its influence on the initial drafting of the Indian Constitution.
Discuss the growth of the demand for civil rights in India for the majority of Indians before the advent of Gandhi in Indian politics. Discuss the intellectual origins of the framework of argument that informed the conceptualization of social reforms that led to revolution in India. History of Making of the Indian Constitution: History Drafting Committee, (composition and . Working), Philosophy of the Indian Constitution: Preamble, Salient Features.
How can teacher training (curriculum and practicum) and school curriculum and guidance materials best support effective pedagogy? How can teacher training (curriculum and practicum) and the school curriculum and guidance materials best support effective pedagogy?
