Study of Short Channel Effects on FDSOI MOSFET in Nano Regime -TCAD Simulation

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ISSN (PRINT) :2320 – 8945, Volume -1, Issue -6, 2013

27

Study of Short Channel Effects on FDSOI MOSFET in Nano Regime -TCAD Simulation

Madhusudan Singh¹ & Ashwani K. Rana²

1Dept. of Electronics and Communication Engineering, Shiva Institute of Engineering and Technology Bilaspur, Bilaspur, H.P. India-174004

2 Dept. of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Hamirpur, H.P. India-177005

E-mail : [email protected]¹, [email protected]²

Abstract – CMOS device dimensions are shrinking down due to continuous technology scaling, give rise to short channel effects which results in poor electric performances of CMOS devices and need to be addressed by Researchers in future nano devices. In this decade, Silicon-on-insulator (SOI) technology based CMOS Devices has been offering superiority over Bulk CMOS devices in terms of speed, packaging density, radiation hardness capability. In this work the short channel effects of nano scale SOI based MOSFET has been examined. Variations in channel doping concentration of SOI MOSFET is explored to study the impact of channel doping on short channel effects (SCEs) such as threshold voltage fluctuation, leakage current (IOFF), drain induced barrier lowering (DIBL) and subthreshold swing (SS) of n-channel FDSOI MOSFET.

In this work TCAD Device Simulation has been used.

Keywords – Technology CAD (TCAD), density gradient (DG), fully depleted silicon-on-insulator (FDSOI), subthreshold slope (SS), drain induced barrier lowering (DIBL).

I. INTRODUCTION

To achieve valuable VLSI constraints i.e. area, delay and power optimization, the dimensions of the device has been scale down for the past few decades. So it is become difficult to continue with bulk Devices because of short channel effects problem in sub- nanoregime. Short channel effects (SCEs) are less dominant in SOI technology based MOSFETs but still SOI Devices are suffering with short channel effects such as gate leakage and subthreshold leakage to a less extent due to continuous scaling of threshold voltage (V_TH) and supply voltage (V_DD). So channel doping optimization is one of the options to control short channel effects and electrical performance

improvement. Reduced capacitance enhances the SOI Device speed and buried oxide layer (BOX) provide better isolation thereby makes charge leakage impossible. Small capacitance makes SOI devices attractive for low power, low voltage (LP/LV) application and accepted as better option for gate length <50nm in nano regime. But SOI Devices are suffering from self heating effect and floating body effect. In this paper, we will present detailed analysis of n-channel fully depleted SOI MOSFET channel doping variations. The three governing equations for charge transport in semiconductor devices are the Poisson equation and the electron and hole continuity equations.

The Poisson equation is:

) 1 ( ...

)

( p n N

_D

N

_A _trap

q 



       





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Where ε is the electrical permittivity, q is the elementary electronic charge, n and p are the electron and hole densities, N_D is the concentration of ionized donors, N_A is the concentration of ionized acceptors, and ρtrap is the charge density contributed by traps and fixed charges.

The keyword for the Poisson equation is Poisson. The keywords for the electron and hole continuity equations are electron and hole respectively in Sentaurus Simulator. They are written as:

) 2 ...(

...

t q n qR J

_n _net



 







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) 3 ( ...

...

t q p qR J

_p _net



 









(3)

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ITSI Transactions on Electrical and Electronics Engineering (ITSI-TEEE)

28 Where R_net is the net electron–hole recombination rate, J_n is the electron current density and J_p is the hole current density.

II. DESIGNMETHOD

A metal gate technology based simulated tecplot architecture of n-channel fully depleted SOI MOSFET is shown in Fig. 1.

Fig. 1 : Architecture of n-channel FDSOI MOSFET TABLEI

DEVICE PARAMETERS TAKEN FOR DESIGN S.No. Parameter Value [unit]

1. Effective Gate

Length 40 [nm]

2. Gate oxide thickness 2.5 [nm]

3. BOX thickness 25 [nm]

4. Spacer thickness 10 [nm] each side

5. SOI film thickness 10 [nm]

6. Lateral diffusion

(LD) 5[nm] each side

The active region (SOI film) is separated from the substrate by using a buried oxide layer (BOX) which acts as an insulator. The Gate oxide and spacer are made of SiO₂ material in order to reduce fringing field effect.

All simulation is done with the help of Sentaurus Simulator using Density Gradient (DG) carrier transport model. The DG model solves the quantum potential equations to include quantization effects, velocity saturation within high-field regions and mobility

degradation due to high doping concentration and surface roughness scattering in a classical device simulation. The quantum potential is a function of the carrier densities and their gradients in the density- gradient transport approximation. The some other nano- devices such as double gate SOI and tri-gate SOI and nano-wire structures are also simulated with TCAD Simulator. The information regarding to Design of NMOS device Structure is given in table I.

III. RESULTS

The behaviour of fully depleted n-channel SOI MOSFET has been investigated for different channel doping values. Fig. 2 shows the graph between Device Threshold Voltage versus channel doping concentration.

It is observed from the graph that the threshold voltage almost linearly varies with channel doping and control on short channel effects become worse at lower values of channel doping due to reduction in threshold voltage for 40nm channel length SOI NMOSFET.

0.0 2.0x10¹⁷ 4.0x10¹⁷ 6.0x10¹⁷ 8.0x10¹⁷ 1.0x10¹⁸ 0.12

0.16 0.20 0.24 0.28 0.32

Threshold Voltage (V)

Channel doping (cm^-2) VTH

Fig. 2 : Threshold voltage versus Channel Doping concentration

TABLEII

DATA FOR THRESHOLD VOLTAGE AND OFF STATE CURRENT

S.No.

Channel Doping concentration

(cm^-2)

Threshold Voltage

(V)

I_OFF current (A/um)

1. 1.0x10¹⁷ 0.13 6.06x10^-07

2. 2.5x10¹⁷ 0.16 1.85x10^-07

3. 5.0x10¹⁷ 0.19 4.72x10^-08

4. 7.5x10¹⁷ 0.23 1.40x10^-08

5. 1.0x10¹⁸ 0.26 4.38x10^-09

Vertical Direction (um)

Lateral Direction (um)

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0.0 2.0x10¹⁷ 4.0x10¹⁷ 6.0x10¹⁷ 8.0x10¹⁷ 1.0x10¹⁸ 0.0

1.0x10^-7 2.0x10^-7 3.0x10^-7 4.0x10^-7 5.0x10^-7 6.0x10^-7 7.0x10^-7

Leakage current (A/um)

Channel doping (cm^-2) IOFF

Fig. 3 IOFF current versus Channel Doping concentration The values of Threshold Voltage and I_OFF current is given in table II. The graph shown in Fig. 3 represents the effect of variation of channel doping on Leakage current (I_OFF) of the Device. It is clear from the graph, the off state current (I_OFF) increases with decreasing channel doping concentration and for channel doping less than 5 x 10¹⁷ cm^-2, the off state leakage current is become a significant.

0.0 2.0x10¹⁷ 4.0x10¹⁷ 6.0x10¹⁷ 8.0x10¹⁷ 1.0x10¹⁸ 30

45 60 75 90

doping = 8.0 x 10¹⁷

DIBL (mV/V)

Channel doping (cm^-2) DIBL

Fig. 4 : DIBL versus Channel Doping concentration

0.0 2.0x10¹⁷ 4.0x10¹⁷ 6.0x10¹⁷ 8.0x10¹⁷ 1.0x10¹⁸ 78

80 82 84 86

Subthreshold slop (mV/decade)

Channel doping (cm^-2) SS

Fig. 5: Subthreshold slop versus Channel Doping concentration

The behaviour of DIBL and subthreshold slope (SS) is also shown in Fig. 4 and Fig. 5. DIBL first decreases and then increases give a minimum value approximately at channel doping concentration 8 x 10¹⁷. The tendency of subthreshold slop is decreasing with increasing channel doping. At last Fig. 6 presents the drain characteristics of MOSFET for different channel doping concentration. We observed that the electrical performance of the Device in terms of drain current is decreases at higher channel doping concentration due to reduction in carrier mobility with increasing channel doping.

Fig. 6 : Drain Current response at different Channel Doping

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30 IV. CONCLUSIONS

In this paper, performance optimization of a fully depleted n-channel SOI MOSFET has been carried out with the help of channel doping engineering. It is concluded in simulation result that MOSFET threshold voltage increases with increase in channel doping and off state current (I_OFF) decrease as the channel doping concentration increases. However, it is found that minimum DIBL, approximately 45mV/V (Subthreshold slope is also about 81mV/decade) is obtained for channel doping concentration 8x10¹⁷cm^-2. It is observed that the drain current performance of the SOI MOSFET decreases with increase in channel doping concentration due to increased carrier mobility degradation. It is also well known that higher channel doping may lead to carrier mobility degradation in channel which affects the device electrical performance. So we can vary the channel doping concentration upto certain limit.

V. ACKNOWLEDGEMENT

The authors would like to thank Electronics

&Communication Department faculty for their encouragement and support. This work has been done in VLSI Design Laboratory at National Institute of Technology Hamirpur, Himachal Pradesh, India.

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