Positive Feedback Technique for DC-Gain Enhancement of Folded Cascode Op-Amps
Sina Farahmand
ECE Dept., Integrated Circuits and Systems Lab.
K. N. Toosi University of Technology Tehran, Iran
Hossein Shamsi
ECE Dept., Microelectronic Research Lab.
K. N. Toosi University of Technology Tehran, Iran
Abstract—In this paper, a novel folded cascode operational amplifier is proposed which improves DC-gain using positive feedback technique. This method does not affect the unity-gain frequency, stability, power dissipation, and output voltage swing of the conventional folded cascode Op-Amp. The proposed Op- Amp was designed in a standard 0.18µm TSMC 1.8V CMOS technology. Simulation results show a DC-gain enhancement of 25dB and 513MHz unity gain bandwidth for the presented Op- Amp. HSPICE simulation results confirm the theoretical estimated improvements.
I. INTRODUCTION
Operational amplifiers (Op-Amps) are one of the fundamental parts of many analog and mixed-signal systems.
Op-Amps are typically used in the closed-loop configurations.
DC-gain of Op-Amps has an important influence on the precision of the circuits. Besides, the increasing demand for high-resolution ADCs and DACs, voltage references, and sample-and-hold circuits has forced designers to propose novel high-speed and high-gain Op-Amps [1]. In new sub- micron technologies, designing high-gain circuits has become difficult due to low supply and overdrive voltages [2].
To design high-gain Op-Amps with large bandwidth in low-voltage processes, innovative circuit design techniques are required. There are several techniques described in the literature to enhance DC-gain of Op-Amps. One of the conventional approaches to increase DC-gain of folded cascode and telescopic Op-Amps is easily achieved by transistor cascading. Although this approach enhances amplifier output resistance, but leads to limit the output voltage swing [3]. In two-stage Op-Amps, higher DC-gain is achieved by cascading the gain stages. In this method, a proper compensation for stable operation is required. But this compensation will consequently limit the high frequency performance of Op-Amps [4]. Another method which is widely used to enhance DC-gain of Op-Amps is gain-boosting technique [5]. The gain-boosting amplifiers add their own pole and zero to the final Op-Amp and therefore, need a number of external bias voltages and consume more power.
Using positive feedback technique is a well-known method
Figure 1. Circuit schematic of the conventional folded cascode Op-Amp to boost the DC-gain of Op-Amps without limiting the high frequency performance [6]. The main problem of the most positive feedback implementation is a strong dependence of the amplifier’s gain on transistors matching. Bulk driven methods can also be used for signal amplification in low- voltage processes [7, 8]. The principal disadvantage of a bulk-driven MOS device in CMOS technologies is its effective transconductance (gmb), which is 4 or 5 times smaller than gate-transconductance (gm) [1]. Higher circuit noise-level is another drawback of circuits using bulk driven method [9]. In this paper, a new structure is proposed based on the conventional folded cascode Op-Amp shown in figure 1. The proposed Op-Amp uses positive feedback technique for increasing the DC-gain of the conventional Op-Amp without affecting the unity gain bandwidth (UGBW), stability, and power dissipation of the circuit.
This paper is organized as follows: In section II, a brief analysis of the conventional folded cascode Op-Amp is explained. In section III, structure of the proposed Op-Amp is studied in detail. Circuit specifications, such as differential gain and frequency response are calculated in this section.
Section IV is dedicated to simulation results. Device sizes of the proposed Op-Amp are given in this section. Finally section V concludes the paper.
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Figure 2. Circuit schematic of the proposed folded cascode Op-Amp II. CONVENTIOANL FOLDED CASCODE OP-AMP
Figure 1 shows a schematic of the fully differential folded cascode Op-Amp. The folded cascode Op-Amp is a high performance Op-Amp which is widely used in many applications. The differential DC-gain of the Op-Amp is calculated as:
0 1,2
o+ o
v m out
in+ in
V V
A = g R
V V
−
−
− ≈
− (1) where gm1,2 is the transconductance of input devices and Rout is the single ended output resistance obtained as:
7,8 7,8 9,10 3,4 3,4 1,2
[ ] [ ( )]
out m ds ds m ds ds ds
R ≈ g r r & g r r 5 , 6 &r (2)
where gmx and rdsx are the transconductance and the output resistance of the Mx transistor, respectively.
The voltage transfer function of the folded cascode Op- Amp is determined as:
0
(1+ )× (1+ )
V V
a b
A = A
S S
P P
(3)
where the poles Pa and Pb are defined as follows:
1
a
out out
P = R C (4)
1, 2 5, 6 3, 4
3, 4
1
[ 1 ]
b
ds ds n
m
P =
r r ×C
& &g
(5)
in which Cout = CL + Cd(M3,4) + Cd(M7,8) and Cn3,4 denotes all parasitic capacitances of the nodes n3 and n4.
The DC-gain of the conventional folded cascod Op-Amp, with minimum chosen length for all transistors in a standard 0.18µm CMOS technology, is not enough for many specific applications such as pipeline ADC and sample-and-hold circuits. To increase the DC-gain of the conventional folded cascode Op-Amp, a new method based on positive feedback technique is proposed in section III.
Figure 3. Small signal model of left side of the proposed Op-Amp
III. PROPOSED FOLDED CASCODE OP-AMP a. Differential Mode Gain
Circuit schematic of the proposed Op-Amp is shown in figure 2. The CMFB and biasing circuit are not shown for simplicity. In the proposed circuit, the connection paths between transistors M12 and M13 to the transistors M14 and M15
are connected to the gate of cascode transistors M3 and M4. This is to provide a positive feedback loop inside the Op-Amp.
Besides, the CMFB circuitry corrects the offset voltage at the output of the proposed Op-Amp. To calculate the differential mode gain, the small signal analysis of the proposed Op-Amp should be explained carefully. In Fig. 2, the voltages at nodes n1 and n2 are the scaled down version of Vout- and Vout+ by a factor of1/(gm7,8r )o7,8 . The voltages at nodes x1 and x2 shown in Fig. 2, represent the gate voltages of cascode transistors which are defined as:
12,13 1,2
14,15 7,8 7,8
× 1
m
x o+,- o+,-
m m ds
V = g V kV
g g r = (6)
Figure 3 shows left-side small signal model of the proposed Op-Amp. The voltage at node n3 is approximately calculated as equation (7) by applying KCL at node Vo- .
3
3
3 3
1
3 3
1 +
1+
ds m ds
o '
n o- o-
m ds
- kg r r
V = R V = k V
g r (7) where Ro1 is defined as equation (8).
1 7 7 9
12
( 1 )
o m ds ds
m
R = g r r
&g (8)
It should be highlighted that transistor M12 is carefully designed to have an extremely low gmand consequently does not decrease Ro1. The differential mode gain of the proposed Op-Amp is defined using the equation (6) and also applying KCL at node n3, as is introduced in equation (9). According to the differential mode gain of the conventional folded cascode Op-Amp and the proposed one, it is clearly understood that a few expected changes are occurred which have significant effects on the positive feedback loop-gain and stability of the proposed Op-Amp.
1
1 5 1
1 1
( )
o+ o
vd m '
in+ in
ds ds o
V V
A = = g
V V k
r r +R
−
−
−
−
&
(9)
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Figure 4. DC-gain comparison between the propose Op-Amp
Figure 5. Phase margin comparison between the propo Op-Amp
To simplify estimation of the proposed Op- response in the next subsection, it is a differential mode gain of the proposed Op-Am equation (10).
vd m1 out
f
A g R
= K where Rout is the single ended output r conventional folded cascode Op-Amp which the equation (2), and parameter Kf is determin
1 5 1
( 1 )
'
f out
ds ds o
K R k +
r r R
= &
A desirable value for the positive feedback achieved using appropriate sizes for the tran M14, and M15. Due to the equation (10), should be taken a value between zero and o DC-gain of the proposed Op-Amp.
B. Frequency Response
The proposed Op-Amp has several pole two first dominant poles are important in frequency response. In order to simplify the assumed that the Op-Amp consists of forwa paths with individual transfer functions transfer function of the forward path is determ
(1 + ) × (1 + )
f vf
a b
A = A
S S
P P
where Af = gm1,2 Rout . Moreover, the pole determined same as the equations (4) and (5)
ed and conventional
osed and conventional
-Amp’s frequency assumed that the
mp is described as
(10) resistance of the h is calculated in ned as:
(11) loop-gain can be nsistors M12, M13,
the Parameter Kf
ne to increase the
es and zeros, but estimation of the calculations, it is ard and backward as follows. The mined as:
(12)
es Pa and Pb are , respectively.
TABLE I. TRANSISTOR SIZES USE CONVENTIONAL OP
Transistor (W/L) Tran M₁, M₂ 10×10µm / 0.18µm M₉ M₃, M₄ 4×3µm / 0.18µm M M₅, M₆ 4×3µm / 0.18µm M₁₂ M₇, M₈ 10×10µm / 0.18µm M₁₄ The transfer function of the back equation (13), where ( 1 - Af Ab ) = K is described in equation (14).
(1 +
b vb
c
A = A S P
,13 14,15
1
[ 1 ]
c o
m
P =
r1 2 &g
In the equation (14), Cx1,2
capacitances of the nodes x1 and x equations (5), (14) and since gm Pa << Pc << Pb . According to the p and using the equations (12) and function of the proposed Op-Amp is o
1, 2 ×
1 (1 + )
m out
vf v
vf vb f
f a
g R
A = A
- A A K S
K P
≈
It is clearly understood that a zer of the second dominant pole a cancellation [10]. In other words, positive feedback path is cancelled b stability of the Op-Amp is not af transfer function is calculated as:
1, 2 ×
(1 +
m out v
f
f
g R
A K S
K
≈
It is clearly understood that the Op-Amp is determined and changed parameter Kf. As it is described in th parameter Kf should be taken a valu One of the important issues in des Amp is that, the parameter Kf shou close to zero. Otherwise, it can be variations and leads Op-Amp to be proposed Op-Amp should be caut corners of fabrication process.
IV. SIMULATION RE The proposed Op-Amp is design TSMC 1.8V level 49 CMOS proces for both proposed and conventional are chosen identically for fair compa Frequency responses of the prop different process corners are shown compared with the frequency respo folded cascode Op-Amp.
ED IN BOTH PROPOSED AND P-AMP
nsistor (W/L)
₉, M₁₀ 4 ×6µm / 0.18µm M₁₁ 7 ×10µm / 0.18µm
₂, M₁₃ 2.5µm / 0.18µm
₄, M₁₅ 0.6µm/ 0.18µm kward path is calculated in Kf and Pc denotes a pole as
)
c
(13)
]×Cx1, 2
(14)
represents all parasitic x2. In practice, due to the m14,15<< gm3,4 , we have
positive feedback concept (13), the overall transfer obtained as:
(1 + )
) × (1 + ) × (1 + )
c
c b
S P
S S
P P
(15)
ro occurs at the frequency and leads to pole-zero
a pole produced by the y a zero and therefore, the ffected. Hence, the total
1
) × (1 + )
f a b
S S
P P
(16) stability of the proposed by different values of the he previous subsection, the ue between zero and one.
signing the proposed Op- uld not be adjusted very e negative due to process come unstable. Thus, the tiously simulated in the ESULTS
ned in a standard 0.18µm ss. The size of transistors folded cascode Op-Amps rison and listed in Table I.
posed Op-Amp in three in figure 4, 5 and also are onse of the conventional
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Figure 6. Flip-around sample-and-hold circuit with illustration of non- overlapping clock signals
Figure 7. Step response comparison of proposed and conventional folded cascode Op-Amps
The proposed method increases the DC-gain of the Op-Amp about 25dB and does not change the UGBW. In Table II, specifications of the proposed Op-Amp in three process corners are summarized and compared with the conventional Op-Amp. The value of power dissipation and UGBW in Table II are given with CMFB circuitry. Compared to the Op-Amp presented in [8], the proposed Op-Amp has lower circuit complexity, lower power dissipation, and more DC-gain improvement in lower process with minimum chosen length for all transistors which leads to lower chip area.
The proposed and conventional folded cascode Op-Amps are used in a switched-capacitor flip-around sample-and-hold circuit shown in Fig. 6 to compare the steady state error of them. Figure 7 illustrates the circuit level simulation result of a large signal transient response of the both Op-Amps to a 1V (p-p) input step voltage with two non-overlapping clocks at frequency of 25Mhz. As is clear, the proposed Op-Amp reaches 99.944% of input signal final value at the end of holding period, while the output voltage of the conventional folded cascode is 99.406% of input signal at the same time.
TABLE II. SPECIFICATIONS OF THE CONVENTIONAL AND PROPOSED FOLDED CASCODE OP-AMP
Specification Conventional Op-Amp
Proposed Op-Amp TT
(27°C)
FF (-40°C)
SS (85°C) TT (27°C)
Technology 0.18µm 0.18µm 0.18µm 0.18µm
Supply Voltage 1.8V 1.8V 1.8V 1.8V
UGBW 513MHz 513MHz 605MHz 470MHz
DC Gain 51dB 76dB 69dB 83dB
Output Voltage Swing
1.6V 1.6V 1.5V 1.55V
Phase Margin 75.5° 75° 78° 72°
Power Dissipation
2.2mw 2.1mw 2.2mw 2.05mw
Slew Rate 506V
μsec 516
Vμsec
534 Vμsec
495 Vμsec
CL 1pF 1pF 1pF 1pF
V. CONCLUSIONS
In this paper, a new folded cascode Op-Amp is presented which uses positive feedback technique to enhance the DC-gain. The proposed circuit increases the DC-gain of the conventional Op-Amp about 25dB. Simulation results prove that the utilized technique does not affect the speed, output voltage swing, stability, and power dissipation of the conventional folded cascode Op-Amp.
REFERENCES
[1] B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, New York, USA, 2001.
[2] B. l. Blalock, P. E. Allen, G. A. Rincon-Mora, “Designing 1V OP- Amps using standard digital CMOS technology,” IEEE Trans. on Circuits and Syst. II, vo1.45, no.7, pp.769-780, July 1998.
[3] K. Gulati, and H. Lee, “A high-swing CMOS telescopic operational amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998.
[4] K. Bult, and G. Geelen, “A fast-settling CMOS Op-Amp for SC circuits with 90-dB DC gain,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp.
1379-1384, Dec. 1990.
[5] S. Li, and Q. Yulin, “Design of a fully differential gain-boosted folded- cascode Op Amp with settling performance optimization,” in Proc. of IEEE Conference on Electron Devices and Solid-State Circuits, pp.
441-444, Dec. 2005.
[6] H. Mirzaie, H. Khameh, and H. Shamsi, “New two-stage Op-Amp using gate-driven, and positive feedback techniques,” in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1140-1143, Dec. 2010.
[7] H. Khameh, H. Mirzaie, and H. Shamsi, “New two-stage Op-Amp using hybrid cascode compensation, bulk-driven, and positive feedback techniques,” in Proc. Of 8th IEEE International NEWCAS Conference, pp. 109–112, Jun. 2010.
[8] A. Dadashi, Sh. Sadrafshari, Kh. Hadidi, and A. Khoei, “An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35µm CMOS process,” Analog Integrated Circuits and Signal Processing, vol.67, no.2, pp. 213–222, Oct. 2010.
[9] R. S. Assaad, and J. Martinez, “The recycling folded cascode: a general enhancement of the folded cascode amplifier” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, sep. 2009.
[10] P. Grybos, M. Idzik, K. Swientek, and P. Maj, “Integrated charge sensitive amplifier with pole-zero cancellation circuit for high rates,” in Proc. of IEEE Internatioanl Symposium on Circuits and Systems (ISCAS), pp. 1991-2000, 2006.
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