3.3 Instantaneous power consuming level shifter for body implantable buck converter
3.3.3 Driver for body implantable converter
The PCE and the size are the main parameters of a converter used in body implantable devices.
Another important parameter is the tolerance of the input voltage variation. As mentioned earlier, a switching converter uses a driver circuit to control the power MOS switch. The three commonly used techniques are bootstrapping, high-side ground method, and using a standalone level shifter.
Bootstrapping and the high-side ground method have the advantage of low power consumption using a low voltage inverter chain. The level shifter has the advantage on not using external storage capacitor. In this section, a level shifter driver that realizes low power consumption by controlling the instantaneous flowing current similar to a digital inverter is introduced.
The proposed instantaneous power consuming level shifter is shown in Fig.3.35. The methodology to reduce power consumption was proposed for low power high voltage flat panel display driver in [3.62]. The instantaneous power consuming level shifter driver reduces power consumption considerably by controlling the flowing currents IF and IR only at the transition period. A combination of two signals from a microcontroller controls the operation of the driver. However, it is difficult to use a microcontroller for a body implantable device because it increases the size of the device and there is only one feedback signal to control the driver of a switching converter. Hence, an embedded controller for instantaneous power consuming level shifter using a single feedback signal is needed.
Fig.3.35(b) shows the block diagram of a controller for the proposed level shifter for a switching converter. The controller is composed of an edge detector, a delay cell, and an output voltage detector.
The edge detector and delay cell are used to operate the level shifter during the transition period of the input signal. Fig.3.35(c) shows the timing diagram of the controller. The edge detector detects the rising edge of the input signal (VIN) to turn on the falling signal of the level shifter (VFL). The delay cell is used to turn VFL off after a certain time delay. To control the rising signal of the level shifter (VRS), the edge detector and delay cell are used in a manner similar to controlling VFL by detecting the falling edge of VIN.
The current IRS, which controls the rising time of the level shifter output voltage (VOUTH) can be very low because it only charges the gate capacitance of MP3 and MP4. However, IFL, which controls the falling time of VOUTH should be high because it discharges a considerably large output capacitance.
The current source I3 is set from the relation of the switching frequency and output capacitance. I3 draws the charge stored in the output capacitance through MP5. To regulate the voltage drop, a diode connected MP6 is used. IFL is divided into the current through MP5 (IMp5), which is related to the inevitable switching loss, and the current through MP6 (IMp6), which is related to the driver loss.
Fig.3.36 shows IMp5 and IMp6 for varying values of VOUTH. The sum of IMp5 and IMp6 is I3. IMp5 discharges the charge stored in the output capacitance and IMp6 increases as IMP5 decreases. When IMp5
is halved, the consumed power is as high as the switching loss (Psw). From this point, the driver
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consumes more power to fully turn on the power switch. The driver loss (Pdr) includes extra power consumption due to the delay margin of the delay cell (tdm). To increase the PCE, an output voltage detector is used to eliminate extra power consumption.
(a) (b)
(c)
Fig.3.35. Proposed level shifter: (a) schematic, (b) controller, and (c) timing diagram.
Fig.3.36. Detailed waveforms of IFL and VOUTH.
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The output voltage detector is composed of current mirror, diode connected transistor, and comparator. The transition of VOUTH is sensed by the current mirror. When VOUTH falls, MP8 supplies current to MN3, then VOUTL increases. When VOUTL is higher than the reference voltage, the comparator triggers the ending signal to turn the level shifter off. If the transition of VOUTH becomes higher than the threshold voltage required to turn on the power switch before the time delay of the delay cell, the output voltage detector controls VFL to turn the level shifter off. In the case of low supply voltage, VOUTH does not vary sufficiently to be detected by the output voltage detector. In this case, the level shifter is turned off by the delay cell. Hence, the level shifter operates in a wide input range using a combination of the output voltage detector and delay cell. Monte Carlo simulation of the proposed level shifter was performed with 600 samples resulting in output voltage error of 0.1%.
The power distribution of buck converter with conventional and proposed level shifter driver is shown in Fig.3.37. Simulation was conducted when the load current is 3 mA. The result shows that the load with proposed level shifter occupies more portion because power consumption of level shifter is reduced by 66%. In Fig.3.38, efficiency of buck converter on various load with and without proposed level shifter is shown. The efficiency is increased by the maximum of 9% when the load is lightest.
Fig.3.37. Simulated power distribution of the buck converter with conventional and proposed level shifter.
Fig.3.38. Simulated efficiencies of the buck converter with conventional and proposed level shifter driver.
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