2.5 Technical challenges in WPT
2.5.3 Power loss in receiver circuits
The power loss in circuits of wireless power transfer system contributes to degradation in total power conversion ratio from the power supply to the load. Although each of circuit has good power conversion characteristics, the amount of power loss can be significant because power conversion ratio of circuits keeps being multiplied. Since circuits in receiver for wireless power transfer system has identical types of power loss, power loss in buck converter is analyzed. Fig.2.20 shows the switch stage of synchronous buck converter. The main power loss arises due to the power MOSFET switches.
The power loss in the switches can be described as combination of the switching loss (PSW) and the MOSFET’s conduction loss (PCOND) :
+3abc,; = +bd+ +KafF (2.7)
where PMOSFET is total power loss in MOSFET. Conduction loss is caused when switch is on. The current which is conducted through on-resistor of MOSFET occurs conduction loss. To reduce conduction loss, on-resistance need to be reduced. The on-resistance of MOSFET is inversely proportional to the size of the MOSFET. Therefore, conduction loss can be reduced by increasing size of MOSFET.
Fig.2.20. Switch stage of synchronous buck converter.
Fig.2.21. Timing diagram of high-side switch.
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Switching loss occurs during switching transitions. During the transitions of the MOSFET switches, its parasitic capacitance is charged and discharged continuously. Since the parasitic capacitance is dependent on the size of the MOSFET, the switching losses are proportional to the size of the MOSFET. A timing diagram of drain-to-source voltage and current over a period is shown in Fig.2.21.
In the timing diagrams, conduction loss occurs in gh whereas switching loss occurs in gI + g1, and gi + gj. Since voltage characteristic for high-side and low-side MOSFET are different, their loss derivation should be calculated separately.
High-side losses is comprised of switching loss and conduction loss as mentioned. The high-side conduction loss is derived as
+KafF= 5ak;1 × NFb(af) × lmno
lpq (2.8) where IOUT is output current, VOUT is output voltage, VIN is input voltage, RDS(ON) is the on-time drain- to-source resistance of the high side MOSFET and VOUT/VIN is conversion ratio of buck converter.
Switching loss is occurred in turn-on, and turn-off period. For the case of turning the MOSFET switch on, drain current (5F) is rising linearly while voltage across the drain-to-source of MOSFET drops by the value determined by on-resistance. For the case of turning the MOSFET switch off, the current and the voltage are changed opposite as in turn-on phase. By combining turn-on and turn-off power losses, the total switching power loss in high-side MOSFET is derived as
+bd = (lpq×rmno
1 )(2bd)(gb(WsHstu)+ gb(vwxxstu)) (2.9)
where fSW is switching frequency, gb(WsHstu) is the rising time, and gb(vwxxstu) is the falling time. The transition time is proportional to the value of parasitic capacitance. Therefore, low switching loss is achieved in small size of switch. As we analyzed above, conduction loss and switching loss has opposite phenomenon. Thus, optimization between each loss is needed.
Likewise, total power loss in low-side MOSFET can be calculated with the same method from high-side MOSFET. Conduction loss for low-side MOSFET can be calculated as
+KafF = 1 − y ×5ak;1 × NFb(af) (2.10)
where D is duty ratio. The equation is almost same as in high-side MOSFET. However, switching loss is a little different. A drain-source voltage (0Fb) is voltage drop across inherent diode when current is conducted. The forward biased diode voltage is under 0.7 V. It is relatively lower than input voltage.
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Therefore, switching loss in low-side MOSFET can be neglected.
In addition to conduction loss and switching loss in MOSFET, there are few additional losses which is normally much smaller but should be taken into account in low power transfer system. The first additional loss is the power consumed in gate driver of MOSFET switch. Fig.2.22 shows simplified equivalent circuit of gate driver, and MOSFET switch. To calculate power loss in gate driver, the power required to charge the gate capacitance should be considered first :
+z{;, = Gz × 0FF × 2bd (2.11)
where PGATE is power consumption in the gate, Gz is the amount of charges required to turn the MOSFET on or off, and 0FF is the supply voltage of gate driver. The driving loss occurs in transition period of MOSFET switch. The driving loss in rising transition (PDR(rising)) can be derived as :
+F6(WsHstu) =|}~o × 6ÄÅpÇÅ(ÉnÑÑÖnÉ)
16omo~Ñ (2.12) where RDRIVER(PULL-UP) is resistance of pull-up resistor, and RTOTAL is resistance combination of driver output resistance (Rdriver) and gate input resistance (Rgate). The driving loss in falling transition (PDR(falling)) can be derived as :
+F6(vwxxstu)=|}~o × 6ÄÅpÇÅ(ÉnÑÑÖÄmÜq)
16omo~Ñ (2.13) where RDRIVER(PULL-DOWN) is resistance of pull-down resistor.
Fig.2.22. Equivalent circuit of gate driver, and MOSFET switch.
42 Therefore, the total power loss in the driver (PDRIVER) is :
+F6rl,6 = +F6(WsHstu)+ +F6 vwxxstu (2.14)
The second additional loss is diode conduction loss. Under diode conduction condition, both MOSFETs are off. During this time, the inherent diode in MOSFET conducts current in forward biased condition. The diode conduction power loss (PDIODE) caused during this time is:
+FraF, = D × 2bd × 0c × 5ak; (2.15)
where 0c is the forward biased voltage across the diode.
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