From the steps highlighted previously, the value of the calculated inductance value is less than the measured maximum value (𝐿𝑚𝑎𝑥) as stated in Table 4.5. While the value of 𝐿𝑚𝑎𝑥 can be reduced by either inserting an air gap in the core or decreasing the number of turns [76]. The first approach will reduce core loss while the copper loss will become significant [186]. On the other hand, decreasing the number of turns will reduce the copper weight and volume resulting in a substantial core dissipation [76]. Based on the highlighted drawbacks, the final value of the input inductors and tapped inductors are stated in Table 4.5 and the structure shown in Figure 4.11.
Table 4.5: Inductor design parameters
Inductor Type Parameter Calculated Value Measured Value
Input inductor 𝐿1, 𝐿4 88𝜇𝐻 98.2𝜇𝐻
𝐵𝑝𝑘 0.578𝑇 0.639𝑇
𝑁𝑇 5 5
Tapped inductor 𝐿2 + 𝐿3, 𝐿5+ 𝐿6 31.74𝜇𝐻 35.4𝜇𝐻
𝐵𝑝𝑘 0.332𝑇 0.384𝑇
𝑁𝑇,𝑝 = 𝑁𝑇,𝑆 3 3
166 (a)
(b)
Figure 4.11: Structure of inductor and tapped inductor. (a) input inductor hardware.
(b) tapped inductor hardware.
4.3. Modulation and Voltage Balancing Control Technique
This section presents a modified phase-shifted pulse-width modulation technique that enables the even distribution of the ST modes in the 5L-tapped inductor qZS-NNPC converter topology. The additional switching state that highlights the operating principle of the ST mode has been presented in Table 4.1. Furthermore, a voltage balancing control technique for maintaining the clamping capacitor voltages in the proposed converter topology has been given. Both methods are implemented on a field-programmable gate array (FPGA)-based platform within the hardware-in-loop experimental configuration described in Chapter 6.
EI-76 Lamination
Bobbin Kapton tape
Winding
Primary Winding
Secondary Winding Kapton tape
1 2
3 1
4 2
167
4.3.1. Modulation Technique
The modulation technique used in the proposed converter topology is a phase-shifted sinusoidal PWM (PS-PWM) algorithm. However, due to the tapped inductor quasi-Z-source network in the proposed converter, a shoot-through modulation reference is inserted into an additional zero state, as highlighted in Table 4.1. Therefore, this modulation technique consists of three sinusoidal modulation waveforms for each phase of the topology and four high-frequency carrier waveforms phase-shifted at 900 between each other [189], [190]. The shoot-through modulation references (𝑆𝑇𝑝 and 𝑆𝑇𝑛) are represented by two straight lines at the upper and lower points of the PS-PWM technique, as shown in Figure 4.12.
Figure 4.12: Simulated modified PS-PWM technique.
Three sinusoidal modulating signals per phase (𝑉𝑥𝑟𝑒𝑓; 𝑤ℎ𝑒𝑟𝑒 𝑥 𝑖𝑠 𝑎, 𝑏, 𝑐) and four triangular carrier signals (𝑉𝑡𝑟𝑖1, 𝑉𝑡𝑟𝑖2, 𝑉𝑡𝑟𝑖3, 𝑉𝑡𝑟𝑖4) are compared to activate the different switching states within the NST mode, as illustrated in Table 4.1. Based on this operation, the five voltage levels (i.e., 𝑉𝑑𝑐⁄ , 𝑉2 𝑑𝑐⁄ , 0, −𝑉4 𝑑𝑐⁄ , −𝑉4 𝑑𝑐⁄2) of the proposed converter topology are obtained. The shoot-through modulation references 𝑆𝑇𝑝 and 𝑆𝑇𝑛 are used to generate the shoot-through states within the ST mode of the proposed converter topology. Therefore, evenly distributed shoot- through states with constant width are obtained throughout the output voltage waveform.
Furthermore, the addition of the shoot-through states results in the modification output phase voltage which results in a slight change in the volt-second average because the shoot-through states are not introduced during the normal zero states [190]. Therefore, minimizing the change
𝑉𝑡𝑟𝑖1 𝑉𝑡𝑟𝑖2 𝑉𝑡𝑟𝑖3 𝑉𝑡𝑟𝑖4
𝑆𝑇𝑝
𝑆𝑇𝑛 𝑉𝑥𝑟𝑒𝑓
168 in the volt-second average and ascertaining the reference state, the normal active and normal zero states are reconfigured by shifting the interleaved carriers by half of the 𝐷𝑠𝑡. This implies that each phase of the proposed converter topology applies half of the dc-link voltage more times during the positive and negative half-cycles during normal operation [190].
Figure 4.13(a) shows the logic circuit of the modified PS-PWM strategy of the proposed converter topology. The positive and negative shoot-through modulation references 𝑆𝑇𝑝 and 𝑆𝑇𝑛 are obtained from the three-phase modulating signals. The normal active states and normal zero states are generated by comparing the modulating signal with a carrier signal. While the pulse-width modulation (PWM) signals for the shoot-through state are generated by comparing the either the shoot-through modulation reference (𝑆𝑇𝑝) or shoot-through modulation reference (𝑆𝑇𝑛) and a carrier signal (i.e., 𝑉𝑡𝑟𝑖1). Furthermore, the shoot-through state (i.e., State 6 as presented in Table 4.1) is an additional zero state that is inserted after the normal zero state as illustrated in Figure 4.13(b). The switching pattern is based on considerations of the natural switching states of the proposed converter topology.
According to Table 4.1, each switching state have a direct impact on the clamping capacitor voltages. Based on the nature of the proposed converter topology, the switching pattern of the converter was developed as shown in Figure 4.13(b). The switching pattern begins with a normal zero state (i.e., State 3) with the clamping capacitor voltages (𝑉𝑐𝑥1 & 𝑉𝑐𝑥2) charging and 𝑉𝑐𝑥3 remaining constant. Afterwards, the shoot-through state (i.e., State 6) is inserted in the switching pattern with no impact on the clamping capacitor voltages. During the shoot- through state, the boost mode of the converter topology is activated, the normal active state (i.e., State 1) is inserted into the switching pattern with no impact on the clamping capacitor voltage, as shown in Figure 4.13(b). This is closely followed by another normal active state (i.e., State 2) with the clamping capacitor voltage (𝑉𝑐𝑥1) being charged and clamping capacitor voltages (𝑉𝑐𝑥2 & 𝑉𝑐𝑥3) remain constant. Then, the switching interval of another normal zero state (i.e., State 3.3) with the clamping capacitor voltages (𝑉𝑐𝑥1 & 𝑉𝑐𝑥2) discharging and 𝑉𝑐𝑥3 remaining constant. Also, the shoot-through state (i.e., State 6) is inserted in the switching pattern, due to the slight build in the clamping capacitor voltage (𝑉𝑐𝑥3). Therefore, a switching state that ensures the discharging of the clamping capacitor voltage (𝑉𝑐𝑥3) is inserted, as shown in Figure 4.13(b). In addition, the normal active state (i.e., State 5) is inserted into the switching pattern to complete a switching interval, as shown in Figure 4.13(b). The duty cycle of the shoot-through (ST) mode (𝐷𝑠𝑡) is generated using the indirect dc-link control technique [177].
169 The dc-link voltage control loop consists of an integral controller, which adjusts 𝐷𝑠𝑡 based on the error value between the reference value for of the dc-link voltage (𝑉𝑑𝑐∗) and the measure dc-link voltage (𝑉𝑑𝑐,𝑚) [177].
SA1 SA8
SA2 SA7
SA3 SA5
SA4
SA6 STp
STn
VAref
Vtri1
Vtri2
Vtri3
Vtri4
SB1 SB8 SB2
SB7 SB3 SB5
SB6 SB4 VBref
SC1 SC8 SC2 SC7 SC3 SC5 SC6 SC4 VCref
STp
STn
STp STn (a)