DATA AND INSTRUCTION FORMATS, ADDRESSING METHODS AND MACHINE PROGRAMMING CONCEPTS

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HUMBOLDT-UNIVERSITÄT ZU BERLIN

INSTITUT FÜR INFORMATIK

COMPUTER ARCHITECTURE

Lecture 4

DATA AND INSTRUCTION FORMATS,

ADDRESSING METHODS

AND MACHINE PROGRAMMING CONCEPTS

Sommersemester 2002

Leitung: Prof. Dr. Miroslaw Malek

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TYPES OF INFORMATION, DATA AND INSTRUCTION

FORMATS, ADDRESSING METHODS,

AND MACHINE PROGRAMMING CONCEPTS

INFORMATION TYPES

FORMATS (PDP-11, PowerPC, MOTOROLA 68000, Pentium

examples)

ADDRESSES

ADDRESSING MODES

SIMPLE I/O PROGRAMMING

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SOME BASIC INFORMATION TYPES

Information

Data

Instructions

Numbers

Nonnumeric Data

Fixed-point

Floating-point

Binary

Decimal

(4)

DATA FORMATS

In selecting the number representation the following factors should be taken into

account.

1. TYPES of NUMBERS to be represented e.g., integers, real

numbers, complex numbers

2. The RANGE of VALUES to be encountered

3. The PRECISION of the NUMBER

4. THE COST of HARDWARE required to store and process the

numbers

ASCII – American Standard Committee on Information Interchange (7

bits)

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INSTRUCTION FORMATS

In selecting the instruction format(s) the following factors should be

considered.

1. The number of instructions to be represented.

2. The addressability and addressing modes.

3. The ease of decoding.

4. Type of instruction field (fixed or variable)

5. The cost of hardware required to decode

and execute instructions.

OP-CODE ADDRESS(ES)

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INSTRUCTION FORMATS

OP-CODE

1-ADDRESS 10 BITS 3 BITS 3 BITS

OP-CODE

2-ADDRESS 4 BITS 3 BITS 3 BITS

SRC DST

BRANCH

OP-CODE OFFSET

8 BITS 8 BITS

BRANCH ADDRESS = + 2 x OFFSET

DATA FORMAT

16 BITS

2' s COMPLEMENT

8 BITS 8 BITS

CHARACTER CHARACTER

[ UPDATED PC ]

INSTRUCTION AND DATA FORMATS FOR PDP - 11

Mode R_n

Mode R_n Mode R_n

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BASIC INSTRUCTION FORMAT

& PDP-11 ADDRESS FIELD

OP CODE ADDRESS

ADDRESS

MODE Rn

15 6 5 0

MODE 5 4 3 2 1 0

RN

(RN)+

-(RN)

X(RN)

Register

Autoinc.

Autodec.

Index

(0)

(2)

(4)

(6)

0 0 0 0 0 0

0 1 0 0 0 1

1 0 0

1 1 0 1 1 1

R 0

R ₁

R ₇

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INSTRUCTION FORMATS for PowerPC

0 6 11 16 31

OP code RD/RS RA I16/X

(1)

0 6 11 16 31

OP code RD/RS RA Sub OP code

(2) _RB _OE _Rc

0 6 11 16 31

OP code CRD RB I16

(3) _OPc

0 6 11 16 31

OP code CRD RA

(4) _OPc

9

9 21

RB 0

0 6 11 16 31

OP code crbD crbA (5)

21 crbB

0 6 11 16 31

OP code RS RA

(6)

21

SH MB ME

Sub OP code

RD – Destination Register, RS – Source Register, RA – Additional Register, I16 – Immediate Operand, X – offset value, RB – third Register, CR – Condition Register, XER – Exeption Register, OE/Rc – setting flags, MB – Mask Begin, ME – Mask End, SH – Shift/Rotate, crb – Conditional Register Bit, CDR – Comparing field

0 Rc 26 21 22 Two operand general instruction format Three operand general instruction format Instruction format for comparing I

Instruction format for comparing II

Instruction format for logical operations with the use of crb

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DATA FORMAT for PowerPC

0 8 16 24 32 40 48 56 63

Byte 0 Byte 1 Byte 7

Half word 0 Half word 2

Word 0 Word 4

Double word 0

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION FORMAT for MOTOROLA 68000

Operation Word (First Word specifies Operation and Modes) Immediate Operand (If Any, One or Two Words)

Source Effective Address Extension (If Any, One or Two Words)

Destination Effective Address Extension (If Any, One or Two Words)

SINGLE - EFFECTIVE - ADDRESS

INSTRUCTION OPERATION WORD

GENERAL FORMAT

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PENTIUM INTEGER DATA FORMATS

Byte Signed Integer

7 6 0

Sign

Word Signed Integer

15 14 0

Sign

Doubleword Signed Integer

31 30 0

Sign

Byte Unsigned Integer

7 0

Word Unsigned Integer

15 0

Doubleword Unsigned Integer

31 0 BCD X BCD X BCD X ...

7 4 3 0

BCD Integers BCD BCD BCD BCD BCD BCD ...

Packed BCD Integers

Near Pointer

31 0

Offset or Linear Address

Far Pointer or Logical Address

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PENTIUM GENERAL INSTRUCTION FORMAT

Opcode

Smaller encoding fields can be defined within the primary opcode. These fields define the

direction of the operation, the size of displace-ments, the register encoding, condition codes, or sign extension. The encoding of fields in the opcode depends on the class of operation.

ModR/M and SIB Bytes

• The mod and the r/m form 32 possible values: 8 registers and 24 addressing modes. • The reg/opcode field is either a register number or 3 more opcode bits.

It’s is specified in the primary opcode.

• The r/m field can specify a register as an operand or can be combined with the mod field to encode an addressing mode.

Certain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fully specify the addressing form. The base-plus-index and scale-plus-index forms of 32-bit

addressing require the SIB byte. The SIB byte includes the following fields: • The scale field specifies the scale factor.

• The index field specifies the register number of the index register. • The base field specifies the register number of the base register.

Instruction

Prefixes Opcode ModR/M SIB Displacement Immediate

Up to four prefixes of 1 byte each (optional)

1 or 2 byte 1 byte (if required)

1 byte (if

required) Addressdisplacement 1, 2 or 4 bytes or none

Immediate data 1, 2, or 4 bytes or none

7 6 5 3 2 0 Mod _OpcodeReg/ R/M

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NUMBER OF ADDRESSES

ONE - AND TWO - ADDRESS MACHINES

Instruction Comments

LOAD A

MULTIPLY B STORE T LOAD C

MULTIPLY C ADD T

STORE X

Transfer A to accumulator AC

AC AC x B

Transfer AC to memory location T Transfer C to accumulator AC

AC AC x C

AC AC + T

Transfer result to memory location X

MOVE A, T MULTIPLY B,T MOVE C, X MULTIPLY C, X ADD T,X

T A

T T x B

X C

X X x C

X X + T

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THREE - AND ZERO-ADDRESS MACHINES

MULTIPLY A, B,T MULTIPLY C, C, X ADD X, T,X

T A x B

X C x C

X X + T

PUSH A PUSH B MULTIPLY PUSH C PUSH C MULTIPLY ADD

POP X

Transfer A to top of stack Transfer B to top of stack

Remove A, B from stack and replace by A x B Transfer C to top of stack

Transfer second copy of C to top of stack

Remove C, C from stack and replace by C x C

Remove CxC, AxB from stack, replace by their sum Transfer result from top of stack to X

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ADDRESSING METHODS

ABSOLUTE (DIRECT) ADRESSING

- The address of operand is given explicity as part of the instruction

IMPLIED ADDRESSING

- The address is implied by the instruction (e.g.,in one-address machine, the address of the second operand is implied as being accumulator)

IMMEDIATE ADDRESSING

- The operand is given explicitly as the instruction. No memory

access is required. Also operand could follow immediately after the instruction.

INDIRECT ADDRESSING

- The effective address of the operand is in the register or main memory location whose address appears in the instruction. It can have more than one level.

INDEXED ADDRESSING

- The effective address (EA) of the operand is generated by adding an index register value (X) to the direct address (DA)

- EA = X + DA BASE ADDRESSING

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SELF-RELATIVE ADDRESSING

- Effective address is a sum of a direct address and a program counter contents (PC). EA = DA + PC

AUGMENTED ADDRESSING

- Effective address is a concatenation of the contents of the augmented address register (AAR) and direct address.

EA = AAR || DA

(AAR often specifies a page and DA is an address within this particular page)

BLOCK ADDRESSING

- Address of the first word in the block is given. Length of the block is usually specified in the instruction; or also the last address can be given; or special end-of-block

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PowerPC Family - Consortium of Apple, IBM and

Motorola (announced in 1991)

CPU

Speed*

Instructions

L1 cache

601

60-120 MHz

3 per cycle

32 KB

603

75-160 MHz

2 per cycle

2x8 KB

603e

100-300 MHz

2 per cycle

2x16 KB

604

120-180 MHz

4 per cycle

2x16 KB

604e

150-350 MHz

4 per cycle

2x32 KB

G3

200-450 MHz

3 per cycle

2x32 KB 8-10x bus multiplier

750CX

366-466 MHz

3 per cycle

2x32 KB+ 8x bus multiplier

750CXe

400-700 MHz

3 per cycle

2x32 KB+ 10x bus multiplier

G4

350-600 MHz

19 per cycle**

2x32 KB plus 2 MB L2 cache

7410

466-533 MHz

20 per cycle**

2x32 KB plus 1 MB L2 cache

7450

667-733 MHz

unknown

2x32 KB+ 256K L2+2 MB L3

cache

* as used in Apple

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GENERAL METHODS OF ADDRESSING

OF PowerPC

IMMEDIATE INDEX ADDRESSING MODE

-The effective address of the operand is the sum of the contents of a register named in the instruction and a signed 16-bit offset, X, that is also given in the instruction. In assembly language, the operand is specified in the form X(Rsrc), and the effective address is computed as A_eff = X + [Rsrc], where Rsrc is any of the general purpose

registers R1 through R32.

REGISTER INDEX ADDRESSING MODE

- The effective address of the operand is the sum of the contents of two general purpose registers named in the instruction. The effective address is computed as

A_eff = [Ri] + [Rj]. If zero is used in place of Ri, the value 0 is used instead of the

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METHODS OF ADDRESSING MODES FOR BRANCH

INSTRUCTIONS OF PowerPC

ABSOLUTE

- The target address is given in the instruction

RELATIVE

- The distance between the branch instruction and the target address is given in the instruction

REGISTER INDIRECT

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PDP-11 ADDRESSING MODES

B5B4B3 Decim. NAME SYNTAX MEANING

000 0 REGISTER _R

n EA = Rn

(THAT IS, OPERAND =

[R_n ])

010 2 AUTOINCREMENT _{( R}_n ₎₊ _{EA = [R}_n _];

INCREMENT R_n

100 4 AUTODECREMENT _{- ( R}_n ₎ DECREMENT

EA = [R_n

110 6 INDEX _{X( R}_n ₎ FETCH X;

INCREMENT PC

EA = X + [R_n];

001 1 REGISTER

INDIRECT @Rn EA = [ Rn];

011 3 AUTOINCREMENT

INDIRECT @( R n )+ EA = [[RINCREMENT Rn ]];_n;

101 5 AUTODECREMENT

INDIRECT @-( R n ) _{EA = [[R}DECREMENT Rn;

n ]];

111 7 INDEX INDIRECT @X(R n ) FETCH X;

INCREMENT PC

EA = [X+[R_n]]

EA = effective address

[L] = contents of the location whose address is L (the address L can be that of a main memory location or a register R_n)

[[L]] = L points to a location where the effective address can be found

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PDP-11 ADDRESSING MODES WITH R

_n

= PC

010 2 IMMEDIATE

(AUTOINCREMENT) #N EA = [PC];

Increment PC (That is, operand N follows the intstruction)

011 3 A BSOLUTE

(AUTOINCREMENT INDIRECT)

@#A _{EA = [[PC]];}

Increment PC (that is, EA, which is A, follows the intstr.)

110 6 RELATIVE

(INDEX ) A FINCREMENT PC;ETCH X;

EA = X + [PC] (THAT IS, EA IS A, IT IS SPECIFIED RELATIVE TO PC BY DISPLACEMENT X IN WORD FOLLOWING INSTRUCTION)

111 7 RELATIVE

INDIRECT

(INDEX INDIRECT)

@A FETCH X;

INCREMENT PC;

EA = [X+[PC]];

(THAT IS THE ADDRESS

A OF LOCATION CONTAINING EA IS SPECIFIED RELATIVE TO [PC] BY

DISPLACEMENT X IN WORD FOLLOWING INSTRUCTION)

EA = effective address

[L] = contents of the location whose address is L (the address L can be that of a main memory location or a register R or PC)

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THE 68000 MICROPROCESSOR

ADDRESSING MODES & INSTRUCTIONS

68000, 68020, 68030, 68040 & 68060 (two architectures)

•16-bit external & 32-bit internal - (16 data, 24 address) 64 pins

(other models have 32 data and 32 address)

•32, 16 & 8 bit words (operands)

31 16 15 7 0

byte word

long word

8 DATA REGISTERS, 8 ADDRESS REGISTERS (A USER STACK POINTER, SUPERVISOR STACK POINTER) PROGRAM COUNTER

STATUS REGISTER (supervisor or trace mode select,

interrupt mask, X extended, N negative, Z zero, V overflow, C carry) byte 0 byte 1

byte 2 byte 3

byte 224 _{- 2} _{byte 2}24_{- 1}

long word 0 long word 4 0

2

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PENTIUM ADDRESSING MODES

Process or Word and Bus Widths of some

16, 16/32 and 64/32 Bit CISC Microprocessors