In the early years of the course, we hand-wired modules consisting of discrete transistors to implement our designs. All Verilog code in this textbook is tested using the Modelsim simulator.
Acknowledgments
Combinational Logic
The behavior of a combinational logic circuit can be specified by a truth table that gives the circuit outputs for each combination of input values. A logic function can also be represented in terms of the inputs for which the function value is 0.
Boolean Algebra and Algebraic Simplification
Each of the terms in the Product of Sums (POS) expression in (1‑4) is called a maxterm, and (1‑4) is called a maxterm expansion. Use the statement X 1 XY 5 X to eliminate redundant terms if possible; Then try to apply the consensus theorem (XY 1 X9Z 1 YZ 5 XY 1 X9Z) to eliminate any consensus terms.
Karnaugh Maps
Karnaugh mapping techniques can be extended to simplify functions such as this by using mapped variables. This expression will be a minimum sum provided that the values of the variables entered in the map can be assigned independently.
Designing with NAND and NOR Gates
Even if the AND and OR gates are not interchanged, we can still convert the AND and OR circuit into a NAND or NOT circuit, but additional inverters may need to be added so that each inversion added is canceled by another inversion. Convert all AND gates to NAND gates by adding an inversion bubble at the output.
Hazards in Combinational Circuits
Alternatively, you can start with a product of sums expression in which each pair of adjacent 0s is covered by a 0 term. Similarly, a static 0 hazard can be identified by writing a product of sums expression for the circuit.
Flip-Flops and Latches
Two NOR gates can be connected to form an unclocked S-R (set-reset) flip-flop, as shown in Figure 1-14. In this case, Q1 represents the state after any input changes have propagated to the Q output.
Mealy Sequential Circuit Design
The next step is to make a state assignment that relates the flip-flop states to the states in the table. Realize the flip-flop input equations and output equations using the available logic gates.
Design of a Moore Sequential Circuit
Note that Z depends only on the flip-flop states and is independent of X, whereas for the corresponding Mealy machine, Z was a function. It was equal to AX). In contrast, for the RZ (return to zero) code, 0 is transmitted as 0 for a full bit time, but 1 is transmitted as 1 for the first half of the bit time, and then the signal is returned to 0 for the second half.
Equivalent States and Reduction of State Tables
If the outputs associated with states i and j are different, place a 3 in square i–j to indicate that i ò j. the outputs are the same, place the implicit pairs in square i–j. If the output and next states are the same (or if i–j only suggests itself), check (√) in square i–j to indicate that i ; j.
Sequential Circuit Timing
- Propagation Delays, Setup, and Hold Times
- Timing Conditions for Proper Operation
- Glitches In Sequential Circuits
- Synchronous Design
Assuming that the next active edge of the clock comes after the setup time has elapsed, the output of the flip-flop will change to 0. Assume that the setup and hold times of the flip-flop are 4 ns and 2 ns.
Tristate Logic and Busses
On the other hand, synchronous design has several disadvantages: In high-speed circuits where the propagation delay in the wiring is significant, the clock signal must be carefully routed so that it reaches all the clock inputs at essentially the same time (i.e., minimizes clock skew). So, if Enb 5 Ldc 5 1, the data in register B will be copied to register C when the active edge of the clock occurs.
Problems
Check that the output of the flip-flop changes to D after the rising edge of the clock. The setup time of the flip-flop is 10 ns and the hold time is 5 ns.
Introduction to Verilog®
Computer-Aided Design
Once the functionality of the design has been verified through simulation, the next step is synthesis. The design is mapped to a specific target technology and placed into specific parts of the target ASIC or FPGA.
Hardware Description Languages
In the case of Verilog, if you already know another hardware description language, it is good to compare it with Verilog, but you should be careful when comparing it with languages like C. VHDL and Verilog have a completely different purpose than languages like C, and a comparison with C is not a useful activity.
Verilog Description of Combinational Circuits
The expression is evaluated when the statement is executed, and the signal on the left side is scheduled to change after delay. Then the 1 goes back to the input and the output changes to 0 after the inverter delay.
Verilog Modules
Note that the order of the signals in the named connection can be in any order as long as the signals in the module are connected to named ports. All simulation examples in this text use the ModelSim Verilog simulator from Mentor Graphics.
Verilog Assignments
The code in Figure 2-13 will actually compile, simulate, or synthesize in most tools, even if D is only declared as an output. The output mode can also be used as an input in a statement within the same module, but inout must be used as in Figure 2-14 if D is to be used as input and output by other modules.
Procedural Assignments
The variables on the left-hand element of a 5 or ,5 in an always block must be defined as reg data type. D and E must be defined as right since right is the only legal type on the left-hand element of a 5 or .5 in an always block.
Modeling Flip-Flops Using Always Block
In Figure 2-17, notice that D is not in the sensitivity list because changing D will not cause the state of the flip-flop to change. Since RN and SN reset and set the flip-flop independently of the clock, they are tested first.
Always Blocks Using Event Control Statements
The following example will block the flow of the procedural block when the condition of the wait statement is FALSE. Latches can be avoided by adding another clause or by initializing sum and carry to 0 at the beginning of the always statement.
Delays in Verilog
However, an input pulse shorter than the assignment delay does not propagate to the output. Inertial delay is intended to model gates and other devices that do not propagate short pulses from the input to the output.
Compilation, Simulation, and Synthesis of Verilog Code
- Simulation with Multiple Processes (Initial or Always Blocks)
If two non-blocking updates are made to the same variable in the same time step, the other dominates at the end of the time step. In the absence of the initial block, one can force input changes using simulation commands.
Verilog Data Types and Operators
- Data Types
- Verilog Operators
The { } operator can be used to join two vectors (or an element and a vector, or two elements) together to form a longer vector. To | , one of the operands of | must be obtained by the concatenation, which evaluates the expression within the concatenation and applies operators ~,{ } before the | can be evaluated.
Simple Synthesis Examples
Note that C is an internal signal and is therefore not shown in the block diagram. This is because D, the output of the block shown in the figure, is never assigned.
Verilog Models for Multiplexers
- Using Conditional Operator
- Using If-else or Case Statement in an Always Block
If all values are not explicitly given, a default clause is required in the case statement. Alternatively, MUX can also be modeled using an if-else statement inside an always: block.
Modeling Registers and Counters Using Verilog Always Statements
Since the register outputs can only change on the rising edge of the clock, CLR and Ld are not on the sensitivity list. On the rising edge of the clock, the counter is reset when ClrN 5 , and incremented when ClrN 5 En 5 1.
Behavioral and Structural Verilog
- Modeling a Sequential Machine
The second always blocks the state register and updates the state at the appropriate edge of the clock. When the rising edge of the clock occurs, State is updated to the value of Nextstate so that CLK appears in the sensitivity list.
Constants
Time to market is an important measure of success in the IC market; so designers often use behavioral design to achieve fast time to market. However, module parameters can be modified at compile time to have values different from those specified in the declaration command.
Arrays
The array construct along with parameter can be used to create look-up tables which can be used to create combinational circuits using ROM or Look-up Table (LUT) method. This can be achieved using the ROM or LUT method using a lookup table of size 16 entries × 5 bits.
Loops in Verilog
The loop index (i) will be initialized to 0 when the for loop is entered and the sequential statements will be executed. The execution from one iteration (Cout) is copied to the carry-in (Cin) before the end of the loop.
Testing a Verilog Model
It may be noted that the test bench module has no external inputs and outputs; therefore, the port list is empty in the module declaration in statement 1. The test module must be instantiated in the test panel outside the always statement.
A Few Things to Remember
$display and $strobe are displayed once each time they are executed (ie, each time the statement is encountered), whereas $monitor is displayed each time one of its parameters is changed. The difference between $display and $strobe is that $strobe displays the parameters at the end of the current simulation time unit.
To design hardware (i.e., to model and synthesize hardware) This is a major use of Verilog, and the following guidelines are important
In Verilog 2001 or later, always use @* to avoid accidentally omitting signals from sensitivity lists. f) When procedural assignments (always block) are used for sequential logic, use non-blocking assignments (eg '<5'). g) Do not mix blocking and non-blocking statements in an always block. h). This is not a compilation error, but it leads to timing problems that are very difficult to debug. i) Avoid unwanted deadlocks by assigning a value to combinational output signals in every possible execution path in the always block.
To model hardware (i.e., to create simulation models which are not necessarily synthesizable) There are several choices in the types of statements used when
It is possible to use procedural assignments (always blocks) to design either combinational logic or sequential logic. e) When procedural assignments (always blocks) are used for combinational logic, use blocking assignments (eg '5'). Verification models and test benches mostly use initial blocks with blocking assignments and delayed assignments (see Figure 2-64.
To verify hardware. Verification models and test benches mostly use initial blocks with blocking assignments and delayed assignments (see Figure 2-64
- Given
- Given
- Given
- Given
- Given
All changes occur on the falling edge of the clock. a) Write a behavioral Verilog description of the counter. Assume that state changes occur 10 ns after the falling edge of the clock and that output changes occur 10 ns after the state change. 2.54 Write Verilog code to implement the following status table.
Introduction to Programmable Logic Devices
Brief Overview of Programmable Logic Devices
Examples of factory-programmable logic are mask-programmable gate arrays (MPGAs) and read-only memories (ROMs). Programmable logic devices basically contain a set of basic building blocks that can be used to implement any desired functionality.
Simple Programmable Logic Devices (SPLDs)
- read-Only Memories (rOM)
- Programmable Logic Arrays (PLAs)
- Programmable Array Logic (PAL)
- Programmable Logic Devices (PLDs)/generic Array Logic (gAL)
The state of the circuit can then be stored in a register D flip-flops and fed back to the ROM input. The basic structure of PAL is the same as PLA shown in Figure 3-9.
Complex Programmable Logic Devices (CPLDs)
- An example CPLD: The Xilinx Coolrunner
The Ad signal can be connected to the enable input (CE) of each flip-flop via an AND gate (not shown). Each bit of the adder requires eight product terms (four for the sum, three for the carry, and one for CE).
Field-Programmable Gate Arrays (FPGAs)
- Organization of FPgAs
- FPgA Programming Technologies
- Programmable Logic Block Architectures
Changing the contents of the SRAM in the arrangement in Figure 3-28(b) will allow the designer to change what is connected to point X. The bits that are stored in the SRAM to set the LUT functionality or interconnect are called configuration bits. a). Typically, what is done is to use the EPROM as a "boot ROM", The contents of the EPROM are transferred to the SRAM when power comes on.
