Introduction to Programmable Logic Devices
3.3 Complex Programmable Logic Devices (CPLDs)
Improvements in integrated circuit technology have made it possible to create pro- grammable ICs equivalent to several PLDs in the same chip. These chips are called complex programmable logic devices (CPLDs). When storage elements such as flip- flops are also included on the same IC, a small digital system can be implemented with a single CPLD.
CPLDs are an extension of the PAL concept. In general, a CPLD is an IC that consists of a number of PAL-like logic blocks together with a programmable inter- connect matrix. CPLDs typically contain 500 to 10,000 logic gates. Essentially, sev- eral PLDs are interconnected using a crossbar-like switch and fabricated inside the same IC. An N 3 M crossbar switch is one in which each of the N input lines can be connected to any of the M output lines simultaneously. It is expensive to build these switches; however, use of such a switch results in predictable timing. Many CPLDs are electronically erasable and reprogrammable and are sometimes referred to as EPLDs (erasable PLDs).
A typical CPLD contains a number of macrocells that are grouped into function blocks. Connections between the function blocks are made through an interconnec- tion array. Each macrocell contains a flip-flop and an OR gate, which has its inputs connected to an AND gate array. Some CPLDs are based on PALs, in which case each OR gate has a fixed set of AND gates associated with it. Other CPLDs are based on PLAs, in which case any AND gate output within a function block can be connected to any OR gate input in that block.
Xilinx, Altera, Lattice Semiconductor, Cypress, and Atmel are the major CPLD manufacturers in the market today. The major products available in the market are listed in Table 3-6. Some vendors specify their gate capacities in usable gates and some specify it in terms of logic elements.
Vendor CPLD Family gate Count
Xilinx CoolRunner-II 750 to 12K
CoolRunner XPLA3 750 to 12K
XC9500XV 800 to 6400
XC9500 800 to 6400
XC9500XL 800 to 6400
Atmel CPLD ATF15 750 to 3000 usable gates
CPLD-2 22V10 500 usable gates
CPLD-Proprietary 2500
Cypress Delta39K 30K to 200K
Flash370i 800 to 3200
Quantum38K 30K to 100K
Ultra37000 960 to 7700
MAX340 high-density EPLDs 600 to 3750
Lattice ispXPLD 5000MX 75K to 300K
ispMACH 4000B/C/V/Z 640 to 10,240
Altera MAX II 240 to 2,210 logic elements
MAX3000 600 to 10K usable gates
MAX7000 600 to 10K usable gates
3.3.1
An example CPLD: The Xilinx Coolrunner
Xilinx has two major series of CPLDs—the CoolRunner and the XC9500. Figure 3-21 shows the basic architecture of a CoolRunner family CPLD, the Xilinx XCR3064XL.
This CPLD has 4 function blocks, and each block has 16 associated macrocells TABLe 3-6: Major CPLDs
and Their Approximate Capacity
(MC1, MC2,...). Each function block is a programmable AND-OR array that is configured as a PLA. Each macrocell contains a flip-flop and multiplexers that route signals from the function block to the input/output (I/O) block or to the intercon- nect array (IA). The interconnect array selects signals from the macrocell outputs or I/O blocks and connects them back to function block inputs. Thus, a signal gen- erated in one function block can be used as an input to any other function block.
The I/O blocks provide an interface between the bidirectional I/O pins on the IC and the interior of the CPLD.
Figure 3-22 shows how a signal generated in the PLA (function block) is routed to an I/O pin through a macrocell. Any of the 36 inputs from the IA (or their com- plements) can be connected to any inputs of the 48 AND gates. Each OR gate can accept up to 48 product term inputs from the AND array. The macrocell logic in this diagram is a simplified version of the actual logic. The first MUX (1) can be programmed to select the OR gate output or its complement. The MUX (2) at the output of the macrocell can be programmed to select either the combinational out- put (G) or the flip-flop output (Q). This output goes to the interconnect array and to the output cell. The output cell includes a 3-state buffer (3) to drive the I/O pin.
The buffer enable input can be programmed from several sources. When the I/O pin is used as an input, the buffer must be disabled.
FUNCTION BLOCK
FUNCTION BLOCK
I/O 36
16 16
36
16 16 MC1
MC2 MC16
I/O MC1
MC2 MC16
FUNCTION BLOCK
FUNCTION BLOCK
I/O 36
16 16
36
16 16 MC1
MC2 MC16
I/O MC1
MC2 MC16 Inter-
connect array
(IA)
I/O Pins
FIgure 3-21: Architecture of Xilinx CoolRunner XCR3064XL CPLD
36 Inputs from IA
D Q
CE CK
1 2 3
Part of PLA Simplified macrocell Output cell Programmable
enable to IA to IA
F G
Programmable select
Flip-flop
I/O pin 1 of 16 OR gates
48 AND gates FIgure 3-22: CPLD
Function Block and Macrocell (Simplified Version of XCR3064XL)
Figure 3-23 shows how a Mealy sequential machine with two inputs, two outputs, and two flip-flops can be implemented by a CPLD. Four macrocells are required, two to generate the D inputs to the flip-flops and two to generate the Z outputs. The flip-flop outputs are fed back to the AND array inputs via the inter- connection matrix (not shown). The number of product terms required depends on the complexity of the equations for the Ds and the Zs.
Q1 Q2 FF
FF FF
AND array X1 X2
Z1 Z2 Macrocells
D1 D2
CPLD Implementation of a Parallel Adder with Accumulator
Assume that we need to implement an adder with an accumulator, as in Figure 3-24, in a CPLD. The accumulator register needs one flip-flop for each bit. Each bit also needs to generate the sum and carry bits corresponding to that bit.
- - -
CLK
cn
CE D
Q9 Q
sn
yn xn
Full
adder - - - xn
CE D
Q9 Q
xi
si
yi ci cn+1 ci+1
Full adder
xi
- - - c3 c2
CE D
Q9 Q
x1
s1
y1 Full adder
x1
CE D
Q9 Q
x2
s2
y2 Full adder
x2
ClrN Ad Accumulator
Register - - -
c1=0
Figure 3-25 shows how three bits of such a parallel adder with an accumulator can be implemented using a CPLD. Each bit of the adder requires two macro- cells. One of the macrocells implements the sum function and an accumulator flip-flop. The other macrocell implements the carry, which is fed back into the AND array. The Ad signal can be connected to the enable input (CE) of each flip-flop via an AND gate (not shown). Each bit of the adder requires eight product terms (four for the sum, three for the carry, and one for CE). For each accumulator flip-flop
Di5 Xi1 5 Si 5 Xi ! Yi ! Ci FIgure 3-23: CPLD
Implementation of a Mealy Machine
FIgure 3-24: N-Bit Parallel Adder with Accumulator
If the flip-flops are programmed as T flip-flops, then the logic for the sum can be simplified. For each accumulator flip-flop
Xi1 5 Xi ! Yi ! Ci Therefore, the T input is
Ti 5 Xi1 ! Xi 5 Yi ! Ci
The add signal can be AND’ed with the Ti input so that the flip-flop state can change only when Ad 5 1
Ti 5 Ad(Yi ! Ci) 5 Ad Yi Ci9 1 Ad Yi9 Ci The equation for carry is
Ci11 5 XiYi 1 XiCi 1 YiCi