Introduction to Programmable Logic Devices
3.2 Simple Programmable Logic Devices (SPLDs)
3.2.2 Programmable Logic Arrays (PLAs)
A programmable logic array (PLA) performs the same basic function as a ROM.
A PLA with n inputs and m outputs (Figure 3-9) can realize m functions of n vari- ables. The internal organization of the PLA is different from that of the ROM. The TABLe 3-2: ROM
Truth Table
AND array
OR array
m Output lines n Input
lines
PLA
k Word lines
...
... ...
FIgure 3-9:
Programmable Logic Array Structure
decoder is replaced with an AND array that realizes selected product terms of the input variables. The OR array OR’s together the product terms needed to form the output functions.
Figure 3-10 shows a PLA that realizes the following functions:
F0 5 om(0, 1, 4, 6) 5 A9B9 1 AC (3-1)
F1 5 om(2, 3, 4, 6, 7) 5 B 1 AC9 F2 5 om(0, 1, 2, 6) 5 A9B9 1 BC9 F3 5 om(2, 3, 5, 6, 7) 5 AC 1 B
The foregoing logic functions contain three variables. In a PLA implementation, each product term in the equation is created first, and then the required product terms are OR’ed using the OR gate. Hence, product terms can be shared while using the PLA. Instead of minimizing each function separately, we want to min- imize the total number of product terms. There are five distinct product terms in the preceding four equations. Figure 3-10 illustrates a PLA with three inputs, five product terms, and four outputs, implementing the four equations. It should be noted that the number of terms in each equation is not important, as long as there are AND gates to generate all the product terms required for all outputs together.
OR array
AC9 B BC9 AC
A B C
AND array
F0 F1 F2 F3 A9B9
Internally, the PLA may use NOR-NOR logic instead of AND-OR logic. The array shown in Figure 3-10 is thus equivalent to the nMOS PLA structure shown in Figure 3-11. Logic gates are formed in the array by connecting nMOS switching transistors between the column lines and the row lines.
FIgure 3-10: PLA with Three Inputs, Five Product Terms, and Four Outputs (Logic Level)
+V +V +V +V
+V +V +V
+V +V
A B C
A9 B9 C9
Inputs
Outputs F0 F1 F2 F3 AC9
B BC9 AC A9B9
Figure 3-12 shows the implementation of a 2-input NOR gate using nMOS tran- sistors. The transistors act as switches, so if the gate input is a logic 0, the transistor is off. If the gate input is a logic 1, the transistor provides a conducting path to ground. If X1 5 X2 5 0, both transistors are off, and the pull-up resistor brings the Z output to a logic 1 level (1V). If either X1 or X2 is 1, the corresponding transistor is turned on, and Z 5 0. Thus, Z 5 (X1 1 X2)9 5 X19X29, which corresponds to a NOR gate. The part of the PLA array that realizes F0 is equivalent to the NOR- NOR gate structure shown in Figure 3-13. After canceling the extra inversions, this reduces to an AND-OR structure.
+V
X1 X2
Z X1 Z
X2
;
A B A C
A B A C
F0 F0
AC9 A9B9
; FIgure 3-11: PLA with
Three Inputs, Five Product Terms, and Four Outputs (Transistor Level)
FIgure 3-12: nMOS NOR Gate
FIgure 3-13: Conversion of NOR-NOR to AND-OR
Source, drain, and gate are the names of the three terminals of the metal oxide semiconductor (MOS) transistor. The gate is the one that is used to control the ON/OFF action. There are two types of MOS transistors, nMOS and
The contents of a PLA can be specified by a modified truth table. Table 3-3 specifies the PLA in Figure 3-10. The input side of the table specifies the product terms. The symbols 0, 1, and – indicate whether a variable is complemented, not complemented, or not present in the corresponding product term. The output side of the table specifies which product terms appear in each output function. A 1 or 0 indicates whether a given product term is present or not present in the corresponding output function.
Thus, the first row of Table 3-3 indicates that the term A9B9 is present in output func- tions F0 and F2, and the second row indicates that AC9 is present in F0 and F1.
Product Inputs Outputs
Term A B C F0 F1 F2 F3
A9B9 0 0 – 1 0 1 0
AC9 1 – 0 1 1 0 0
B – 1 – 0 1 0 1
BC 9 – 1 0 0 0 1 0
AC 1 – 1 0 0 0 1
Next, we will realize the following functions using a PLA:
F1 5 om(2, 3, 5, 7, 8, 9, 10, 11, 13, 15) (3-2) F2 5 om(2, 3, 5, 6, 7, 10, 11, 14, 15)
F3 5 om(6, 7, 8, 9, 13, 14, 15) If we minimize each function separately, the result is
F1 5 bd 1 b9c 1 ab9 (3-3)
F2 5 c 1 a9bd
F3 5 bc 1 ab9c9 1 abd
If we implement these reduced equations in a PLA, a total of eight different prod- uct terms (including c) is required.
Instead of minimizing each function separately, we want to minimize the total number of rows in the PLA table. In this case, the number of terms in each equation is not important, since the size of the PLA does not depend on the number of terms within an equation. Equations (3-3) are plotted on the Karnaugh maps shown in Figure 3-14. Since the term ab9c9 is already needed for F3, we can use it in F1 instead of ab9. The other two 1s in ab9 are covered by the b9c term. This eliminates the need to use a row of the PLA table for ab9. Since the terms a9bd and abd are needed in F2 and F3, respectively, we can replace bd in F1 with a9bd 1 abd. This eliminates the need for a row to implement bd. Since b9c and bc are used in F1 and F3, respectively, we can replace c in F2 with b9c 1 bc. The resulting equations (3-4) correspond to the reduced TABLe 3-3: PLA Table for
Equations 3-1
pMOS. The illustrations in this section use nMOS transistors. A popular tech- nology since the 1990s is complementary MOS (CMOS), where nMOS and pMOS transistors are used together in a complementary fashion.
PLA table (Table 3-4). Instead of using Karnaugh maps to reduce the number of rows in the PLA, the Espresso algorithm can be used. This complex algorithm is described in Logic Minimization Algorithms for VLSI Synthesis by Brayton [10].
a b c d F1 F2 F3
0 1 2 1 1 1 0
1 1 2 1 1 0 1
1 0 0 2 1 0 1
2 0 1 2 1 1 0 2 1 1 2 0 1 1
F1 5 a9bd 1 abd 1 ab9c9 1 b9c (3-4) F2 5 a9bd 1 b9c 1 bc
F3 5 abd 1 ab9c9 1 bc
Because equations 3-4 have only five different product terms, the PLA table has only five rows. This is a significant improvement over Equations 3-3, which require eight product terms. Figure 3-15 shows the corresponding PLA structure, which has TABLe 3-4:
Reduced PLA Table
01
00 11 10
01 00
11 1 1
1 1
1 1
1 1 1
1 1
1 1
1 1
1 1 1 1
1 1 1
1 1 1
10 1
ab
cd 00 01 11 10
01 00
11 10 ab
cd 00 01 11 10
01 00
11 10 ab cd
F1 F2 F3
abd ab9c9
a9bd FIgure 3-14: Multiple-
Output Karnaugh Maps
Inputs
a b c d
Word lines a9bd
abd ab9c9
b9c bc
F1 Outputs
F2 F3 FIgure 3-15: PLA
Realization of Equations 3-4
four inputs, five product terms, and three outputs. A dot at the intersection of a word line and an input or output line indicates the presence of a switching element in the array.
A PLA table is significantly different from a truth table for a ROM. In a truth table, each row represents a minterm; therefore, exactly one row will be selected by each combination of input values. The 0s and ls of the output portion of the selected row determine the corresponding output values. On the other hand, each row in a PLA table represents a general product term. Therefore, zero, one, or more rows may be selected by each combination of input values. To determine the value of F for a given input combination, the values of F in the selected rows of the PLA table must be OR’ed together. The following examples refer to the PLA table of Table 3-4. If abcd 5 0001, no rows are selected, and all Fis are 0. If abcd 5 1001, only the third row is selected, and F1F2F3 5 101. If abcd 5 0111, the first and fifth rows are selected. Therefore, F1 5 1 1 0 5 1, F2 5 1 1 1 5 l, and F3 5 0 1 1 5 1.
Next, we realize the sequential machine BCD to Excess-3 Code Converter of Figure 1-23 using a PLA and three D flip-flops. The circuit structure is the same as Figure 3-8, except that the ROM is replaced by a PLA. The required PLA table, based on the equations given in Figure 1-25, is Table 3-5.
Product Term Q1 Q2 Q3 X Q11 Q21 Q31 Z
Q29 2 0 2 2 1 0 0 0
Q1 1 2 2 2 0 1 0 0
Q1Q2Q3 1 1 1 2 0 0 1 0
Q1Q39X9 1 2 0 0 0 0 1 0
Q19Q29X 0 0 2 1 0 0 1 0
Q39X9 2 2 0 0 0 0 0 1
Q3X 2 2 1 1 0 0 0 1