Introduction to Programmable Logic Devices
3.1 Brief Overview of Programmable Logic Devices
C H A P T E R
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Introduction to Programmable
programmed in the user’s “field” rather than in a semiconductor fab. Often, many may refer to programmable logic to mean devices that are field programmable.
However, there are factory-programmable devices as well. These are generic devices that can be programmed at the factory to meet customers’ requirements.
The programming technology uses an irreversible process; hence, programming can be done only once. Examples of factory-programmable logic are mask-programmable gate arrays (MPGAs) and read-only memories (ROMs). The earliest generations of many programmable devices were programmable only at the factory.
Read-only memories (ROMs) can be considered an early form of programma- ble logic. While primarily meant for use as memory, ROMs can be used to imple- ment any combinational circuitry. This is illustrated subsequently in the section on ROMs. MPGAs are traditional gate arrays, which require a mask to be designed.
MPGAs are often simply called gate arrays and have been a popular technology for creating application-specific integrated circuits (ASICs).
User programmable logic in the form of AND-OR circuits was developed at the beginning of the 1970s. By 1972–73, one-time field-programmable logic arrays that permitted instant customizations by designers were available. Some referred to these devices as field-programmable logic arrays or FPLAs. Monolithic Memories Inc. (MMI), a company that was bought by Advanced Micro Devices (AMD), created integrated circuits called programmable logic arrays (PLAs) in 20–24 pin packages that could yield the same functionality as 5 to 20 off-the-shelf chips. A similar device is the programmable array logic or PAL.
PALs and PLAs contain arrays of gates. In the PLA, there is a programmable AND array and a programmable OR array, allowing users to implement combinational func- tions in two levels of gates. The PAL is a special case of a PLA, in that the OR array is fixed and only the AND array is programmable. Many PALs also contain flip-flops.
Programmable Logic
Field-Programmable Devices Factory-Programmable
Devices
MPGA Mask Programmable
Gate Array ROM
Read-Only Memory
FPGA Field Programmable
Gate Array CPLD
Complex Programmable
Logic Device SPLD
Simple Programmable
Logic Device
PLA Programmable
Logic Array
PAL Programmable
Array Logic
GAL Generic Array Logic PROM
Programmable Read-Only
Memory FIgure 3-1: Major
Programmable Logic Devices
In the 1970s and 1980s, PALs and PLAs were very popular. Part of the popularity was due to the ease of design. MMI and Advanced Micro Devices created a simple programming language, called PALASM, to easily convert Boolean equations into PLA configurations. PALASM made programming PALs and PLAs relatively simple.
The early programmable devices allowed only one-time programming. The next technological innovation that helped programmable logic was advancement in erasure of programmable devices. In the early days, erasure of programmable logic used ultraviolet light. With ultraviolet light, erasing the configuration of a device meant removing the device from the circuit and placing it in an ultraviolet envi- ronment. Hence, in-circuit erasure was not possible. Ultraviolet erasers were slow;
typically 10 or 15 minutes were required to perform erasures. Then electrically eras- able technology came along. This led to the creation of field-programmable logic arrays that can be easily and quickly erased and reprogrammed without removing the chip from the board.
The early PALs and PLAs were soon followed by CMOS electrically erasable programmable logic devices (PLDs). While the term PLDs can be used to refer to any programmable logic devices, there are a set of devices, including the popular PALCE22V10, that are often referred to as PLDs. PLDs contain macroblocks with arrays of gates, multiplexers, flip-flops, or other standard building blocks. Several of these macroblocks appear in a PLD. Lattice Semiconductor created similar devices with easy reprogrammability and called their line of devices GALs (generic array logic).
Now, many refer to PLAs, PALs, GALs, PLDs, and PROMs collectively as simple PLDs (SPLDs) in contrast to another product that has come into the mar- ket, complex PLDs (CPLDs). As the name suggests, CPLDs have more integration capability than SPLDs. They come in sizes ranging from 500 to 16,000 gates. CPLDs essentially put multiple PLDs into the same chip with some kind of an interconnec- tion circuit, typically a crossbar switch.
During the late 1980s, Xilinx started using static RAM storage elements to hold configuration information for programmable devices and created devices called field-programmable gate arrays (FPGAs), which can integrate a fairly large amount of logic. Contrary to their names, the basic building blocks in these devices were not arrays of gates but were bigger and complex blocks containing static RAMs and multiplexers. Several PLD vendors and gate array companies soon jumped into the market creating a variety of FPGA architectures, some of which used reprogram- mable technologies while others used one-time programmable fuse technologies.
The FPGA technology has continually improved during the past 15 years. Now, there are FPGAs that can contain more than 5 million gates.
Programmable logic devices basically contain an array of basic building blocks that can be used to implement whatever functionality one desires. Different pro- grammable devices differ in the building blocks or the amount of programmability they provide. Table 3-1 illustrates a comparison of various programmable logic devices. FPGAs are bigger and more complex than CPLDs. The routing resources in FPGAs are more complex than those in simple programmable devices. The variety of alternate routes that can be taken cause the paths taken by signals to be unpredictable. FPGAs are more expensive than CPLDs and SPLDs. They contain more overhead for programming. In this chapter, we describe various programma- ble devices, including SPLDs, CPLDs, and FPGAs.
SPLD CPLD FPGA
Density Low
Few hundred gates
Low to Medium 500 to 12,000 gates
Medium to High 3,000 to 5,000,000 gates Timing Predictable Predictable Unpredictable
Cost Low Low to Medium Medium to High
Major Vendors Lattice Cypress AMD
Xilinx
Altera Xilinx
Altera Lattice Microsemi Example