1.1 Write out the truth table for the following equation:
F 5 (A ! B) ? C 1 A9 ? (B9 ! C)
1.2 A full subtracter computes the difference of three inputs X, Y, and Bin, where Diff 5 X 2 Y 2 Bin. When X , (Y 1 Bin), the borrow output Bout is set. Fill in the FIGURE 1-55: Four Kinds
of Tristate Buffers
FIGURE 1-56: Data Transfer Using Tristate Bus
truth table for the subtracter and derive the sum‑of‑products and product‑of‑sums equations for Diff and Bout.
1.3 Simplify Z using a 4‑variable map with map‑entered variables. ABCD represents the state of a control circuit. Assume that the circuit can never be in state 0100, 0001, or 1001.
Z 5 BC9DE 1 ACDF9 1 ABCD9F9 1 ABC9D9G 1 B9CD 1 ABC9D9H9 1.4 For the following functions, find the minimum sum of products using 4‑variable
maps with map‑entered variables. In (a) and (b), mi represents a minterm of vari‑
ables A, B, C, and D.
(a) F(A, B, C, D, E) 5 om(0, 4, 6, 13, 14) 1 od(2, 9) 1 E(m1 1 m12) (b) Z(A, B, C, D, E, F, G) 5 om(2, 5, 6, 9) 1 od(1, 3, 4, 13, 14)
1 E(m11 1 m12) 1 F(m10) 1 G(m0) (c) H 5 A9B9CDF9 1 A9CD 1 A9B9CD9E 1 BCDF9
(d) G 5 C9E9F 1 DEF 1 AD9E9F9 1 BC9E9F 1 AD9EF9
Hint: Which variables should be used for the map sides and which variables should be entered into the map?
1.5 Identify the static 1‑hazards in the following circuit. State the condition under which each hazard can occur. Draw a timing diagram (similar to Figure 1‑10(b)) that shows the sequence of events when a hazard occurs.
C A9
D9 C9
G
H
F
1.6 Find all of the 1‑hazards in the given circuit. Indicate which changes are necessary to eliminate the hazards.
b9 d9 b c9
a9c d9
F
1.7 (a) Find all the static hazards in the following circuit. For each hazard, specify the val‑
ues of the input variables and which variable is changing when the hazard occurs.
For one of the hazards, specify the order in which the gate outputs must change.
a b a c a9 d
F 1
2
3
4 5
(b) Design a NAND‑gate circuit that is free of static hazards to realize the same function.
1.8 (a) Find all the static hazards in the following circuit. State the condition under which each hazard can occur.
(b) Redesign the circuit so that it is free of static hazards. Use gates with at most three inputs.
d9 a9 a
b b9 c9
Z
1.9 (a) Show how you can construct a T flip‑flop using a J‑K flip‑flop.
(b) Show how you can construct a J‑K flip‑flop using a D flip‑flop and gates.
(c) Show how you can construct a D flip‑flop using a J‑K flip‑flop and gates.
1.10 Construct a clocked D flip‑flop, triggered on the rising edge of CLK, using two transparent D latches and any necessary gates. Complete the following timing dia‑
gram, where Q1 and Q2 are latch outputs. Verify that the flip‑flop output changes to D after the rising edge of the clock.
CLK D Q1 Q2
1.11 A synchronous sequential circuit has one input and one output. If the input sequence 0101 or 0110 occurs, an output of two successive 1s will occur. The first of these 1s should occur coincident with the last input of the 0101 or 0110 sequence.
The circuit should reset when the second 1 output occurs. For example, input sequence: X 5 010011101010 101101 ...
output sequence: Z 5 000000000011 000011 ...
(a) Derive a Mealy state graph and table with a minimum number of states (six states).
(b) Try to choose a good state assignment. Realize the circuit using J‑K flip‑flops and NAND gates. Repeat using NOR gates. (Work this part by hand.) (c) Check your answer to (b) using the LogicAid program. Also use the pro‑
gram to find the NAND solution for two other state assignments.
1.12 A sequential circuit has one input (X) and two outputs (Z1 and Z2). An output Z1 5 1 occurs every time the input sequence 010 is completed provided that the sequence 100 has never occurred. An output Z2 5 1 occurs every time the input sequence 100
is completed. Note that once a Z2 5 1 output has occurred, Z1 5 1 can never occur, but not vice versa.
(a) Derive a Mealy state graph and table with a minimum number of states (eight states).
(b) Try to choose a good state assignment. Realize the circuit using J‑K flip‑flops and NAND gates. Repeat using NOR gates. (Work this part by hand.) (c) Check your answer to (b) using the LogicAid program. Also use the pro‑
gram to find the NAND solution for two other state assignments.
1.13 A sequential circuit has one input (X) and two outputs (S and V). X represents a 4‑bit binary number N, which is input least significant bit first. S represents a 4‑bit binary number equal to N 1 2, which is output least significant bit first. At the time the fourth input occurs, V 5 1 if N 1 2 is too large to be represented by 4 bits; oth‑
erwise, V 5 0. The value of S should be the proper value, not a don’t care, in both cases. The circuit always resets after the fourth bit of X has been received.
(a) Derive a Mealy state graph and table with a minimum number of states (six states).
(b) Try to choose a good state assignment. Realize the circuit using D flip‑flops and NAND gates. Repeat using NOR gates. (Work this part by hand.) (c) Check your answer to (b) using the LogicAid program. Also use the pro‑
gram to find the NAND solution for two other state assignments.
1.14 A sequential circuit has one input (X) and two outputs (D and B). X represents a 4‑bit binary number N, which is input least significant bit first. D represents a 4‑bit binary number equal to N – 2, which is output least significant bit first. At the time the fourth input occurs, B 5 1 if N 2 2 is negative; otherwise, B 5 0. The circuit always resets after the fourth bit of X is received.
(a) Derive a Mealy state graph and table with a minimum number of states (six states).
(b) Try to choose a good state assignment. Realize the circuit using J‑K flip‑flops and NAND gates. Repeat using NOR gates. (Work this part by hand.) (c) Check your answer to (b) using the LogicAid program. Also use the pro‑
gram to find the NAND solution for two other state assignments.
1.15 A Moore sequential circuit has one input and one output. The output goes to 1 when the input sequence 111 has occurred, and the output goes to 0 if the input sequence 000 occurs. At all other times, the output holds its value.
For example,
Derive a Moore state graph and table for the circuit.
X 5 0 1 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 Z 5 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0
1.16 Derive the state transition table and flip‑flop input equations for a modulo‑6 counter that counts 000 through 101 and then repeats. Use J‑K flip‑flops.
1.17 Derive the state transition table and D flip‑flop input equations for a counter that counts from 1 to 6 (and back to 1 and continues).
1.18 Reduce the following state table to a minimum number of states.
Present State Next State Output
X 5 0 X 5 1 X 5 0 X 5 1
A B G 0 1
B A D 1 1
C F G 0 1
D H A 0 0
E G C 0 0
F C D 1 1
G G E 0 0
H G D 0 0
1.19 A Mealy sequential circuit is implemented using the circuit shown in Problem 1.26.
Assume that if the input X changes, it changes at the same time as the falling edge of the clock.
(a) Complete the timing diagram shown here. Indicate the proper times to read the output (Z). Assume that “delay” is 0 ns and that the propagation delay for the flip‑flop and XOR gate has a nominal value of 10 ns. The clock period is 100 ns.
(b) Assume the following delays: XOR gate—10 to 20 ns; flip‑flop propagation delay—5 to 10 ns; setup time—5 ns; and hold time—2 ns. Also assume that the “delay” is 0 ns. Determine the maximum clock rate for proper synchro‑
nous operation. Consider both the feedback path that includes the flip‑flop propagation delay and the path starting when X changes.
(c) Assume a clock period of 100 ns. Also assume the same timing parameters as in (b). What is the maximum value that “delay” can have and still achieve proper synchronous operation? That is, the state sequence must be the same as for no delay.
Clock X Q1 Q2 Z
1.20 Two flip‑flops are connected as shown in the following diagram. The delay rep‑
resents wiring delay between the two clock inputs, which results in clock skew. This can cause possible loss of synchronization. The flip‑flop propagation delay from clock to Q is 10 ns , tp , 15 ns, and the setup and hold times for D1 are always satisfied.
(a) What is the maximum value that the delay can have and still achieve proper synchronous operation? Draw a timing diagram to justify your answer.
D1 Q1 CLK
FF1
Delay
D2 Q2 FF2
(b) Assuming that the delay is ,3 ns, what is the minimum allowable clock period?
1.21 A D flip‑flop has a propagation delay from clock to Q of 7 ns. The setup time of the flip‑flop is 10 ns, and the hold time is 5 ns. A clock with a period of 50 ns (low until 25 ns, high from 25 to 50 ns, and so on) is fed to the clock input of the flip‑flop.
Assume a 2‑level AND‑OR circuitry between the external input signals and the flip‑flop inputs. Assume gate delays are between 2 and 4 ns. The flip‑flop is positive edge triggered.
(a) Assume the D input equals 0 from t 5 0 until t 5 10 ns, 1 from 10 until 35, 0 from 35 to 70, and 1 thereafter. Draw timing diagrams illustrating the clock, D, and Q until 100 ns. If outputs cannot be determined (because of not satisfying setup and hold times), indicate it by XX during the region.
(b) The D input of the flip‑flop should not change between ___ ns before the clock edge and ___ ns after the clock edge.
(c) External inputs should not change between ___ ns before the clock edge and ___ ns after the clock edge.
1.22 A sequential circuit consists of a PLA and a D flip‑flop, as shown in the following diagram.
X
PLA
D Q Z
CLK
0 1 0 1 0 0 1 0 1 1 0 0 1 0 Q+ Z Q
X CLK
Q Z
20 40 60 80 120 ns
(a) Complete the timing diagram assuming that the propagation delay for the PLA is in the range 5 to 10 ns and the propagation delay from clock to out‑
put of the D flip‑flop is 5 to 10 ns. Use cross‑hatching on your timing diagram to indicate the intervals in which Q and Z can change, taking the range of propagation delays into account.
(b) Assuming that X always changes at the same time as the falling edge of the clock, what is the maximum setup and hold time specification that the flip‑
flop can have and still maintain proper operation of the circuit?
1.23 A D flip‑flop has a propagation delay from clock to Q of 15 ns. The setup time of the flip‑flop is 10 ns, and the hold time is 2 ns. A clock with a period of 50 ns (low until 25 ns, high from 25 to 50 ns, and so on) is fed to the clock input of the flip‑flop.
The flip‑flop is positive edge triggered. D goes up at 20, down at 40, up at 60, down at 80, and so on. Draw timing diagrams illustrating the clock, D, and Q until 100 ns.
If outputs cannot be determined (because of not satisfying setup and hold times), indicate it by placing XX in that region.
1.24 A D flip‑flop has a setup time of 5 ns, a hold time of 3 ns, and a propagation delay from the rising edge of the clock to the change in flip‑flop output in the range of 6 to 12 ns. An OR gate delay is in the range of 1 to 4 ns.
(a) What is the minimum clock period for proper operation of the following circuit?
D Q CLK
X
(b) What is the earliest time after the rising clock edge at which X is allowed to change?
1.25 In the following circuit, the XOR gate has a delay in the range of 2 to 16 ns. The D flip‑flop has a propagation delay from clock to Q in the range 12 to 24 ns. The setup time is 8 ns, and the hold time is 4 ns.
D Q CLK
X
(a) What is the minimum clock period for proper operation of the circuit?
(b) What are the earliest and latest times after the rising clock edge at which X is allowed to change and still have proper synchronous operation? (Assume minimum clock period from (a).)
1.26 In the following circuit, the XOR gate has a delay in the range of 2 to 16 ns. The D flip‑flop has a propagation delay from clock to Q in the range 12 to 24 ns. The setup time is 8 ns, and the hold time is 4 ns.
Delay Q1 CK D1
Q2 CK D2
+ +
Clock
X Z
(a) Assume delay 5 0 ns and compute the maximum frequency at which this cir‑
cuit can be safely clocked.
(b) Assume delay 5 5 ns and compute the maximum frequency at which this cir‑
cuit can be safely clocked.
(c) Assume delay 5 –5 ns (i.e., the first flip gets the clock delayed 5 ns as com‑
pared with the second flip‑flop) and compute the maximum frequency at which this circuit can be safely clocked.
(d) Assume delay 5 0 ns and compute the earliest time and latest times after or before the rising clock edge that X is allowed to change and still have proper synchronous operation?
(e) Assume delay 5 5 ns and compute the earliest time and latest times after or before the rising clock edge at which X is allowed to change and still have proper synchronous operation?
(f) Assume delay 5 –5 ns and compute the earliest time and latest times after or before the rising clock edge at which X is allowed to change and still have proper synchronous operation?
1.27 Consider the following circuit where the combinational circuit is represented by COMB and clock skew is represented by tskew.
Clock
CK CK CK
D1 Q1 comb1 D2 Q2 comb2 D3 Q3 tskew1
tskew2
Given the following parameters:
FF setup time 5 20 ns FF hold time 5 10 ns
FF propagation delay 5 5 to 10 ns Tcomb 1 5 5 ns to 7 ns
Tcomb 2 5 6 ns to 11 ns
(a) What is the minimum clock period with tskew1 5 tskew2 5 0?
(b) Now set Tcomb1 5 1 to 4 ns. Is there a setup time violation for the middle flip‑flop? If no, what is the setup time margin?
(c) Now set Tcomb1 5 1 to 4 ns. Is there a hold‑time violation for the middle flip‑flop? If no, what is the hold‑time margin?
(d) What are the minimum values of tskew1 and tskew2 that will fix the violations?
(e) What is the minimum clock period after violations have been fixed?
1.28 Consider the following circuit where the combinational circuit is represented by COMB and clock skew is represented by tskew.
Given the following parameters:
FF setup time 5 10 ns FF hold time 5 2 ns
FF propagation delay 5 12 to 20 ns Tcomb 1 5 5 ns to 7 ns
Tcomb 2 5 6 ns to 11 ns
Clock
CK CK CK
D1 Q1 comb1 D2 Q2 comb2 D3 Q3 tskew1
tskew2
(a) What is the minimum clock period with tskew1 5 0; tskew2 5 3?
(b) Now set Tcomb1 5 1 to 4 ns. Is there a setup time violation for the middle flip‑flop? If no, what is the setup time margin?
(c) Now set Tcomb1 5 1 to 4 ns. Is there a hold‑time violation for the middle flip‑flop? If no, what is the hold‑time margin?
(d) What are the minimum values of tskew1 and tskew2 that will fix the violations?
(e) What is the minimum clock period after violations have been fixed?
1.29 A Mealy sequential machine has the following state table:
PS NS Z
X 5 0 X 5 1 X 5 0 X 5 1
1 2 3 0 1
2 3 1 1 0
3 2 2 1 0
Complete the following timing diagram. Clearly mark on the diagram the times at which you should read the values of Z. All state changes occur after the rising edge of the clock. Assume the machine is initialized to state 1
CLK X PS NS Z
1
1.30 (a) Do the following two circuits have essentially the same timing?
(b) Draw the timing for Qa and Qb given the timing diagram.
(c) If your answer to (a) is no, show what change(s) should be made in the second circuit so that the two circuits have essentially the same timing (do not change the flip‑flop).
D EN
Qa
CLK CLK
EN
D D Qb
CLK EN D EN D
1.31 A simple binary counter has only a clock input (Ck1). The counter increments on the rising edge of Ck1.
(a) Show the proper connections for a signal En and the system clock (CLK), so that when En 5 1, the counter increments on the rising edge of CLK and when En 5 0, the counter does not change state.
(b) Complete the following timing diagram. Explain in terms of your diagram why the switching transients that occur on En after the rising edge of CLK do not affect the proper operation of the counter.
CLK En Ck1 Counter state
1.32 Referring to Figure 1‑56, specify the values of Eni, Ena, Enb, Enc, Lda, Ldb, and Ldc so that the data stored in Reg. C will be copied into Reg. A and Reg. B when the circuit is clocked.