Introduction to Verilog®
3. To verify hardware. Verification models and test benches mostly use initial blocks with blocking assignments and delayed assignments (see Figure 2-64
2.19 Given
reg [7:0] C;
reg signed [7:0] D;
reg [7:0] A = 8'hD5;
evaluate
i. C 5 A .. 4 ii. C 5 A ... 4
iii. C 5 A ,, 4 iv. C 5 A ,,, 4
v. D 5 A .. 4 vi. D 5 A ... 4 vii. D 5 A ,, 4 viii. D 5 A ,,, 4 2.20 Given
reg [7:0] C;
reg signed [7:0] D;
reg [7:0] A = 8'shD5;
evaluate i. C = A >> 4 ii. C = A >>> 4 iii. C = A << 4 iv. C = A <<< 4
v. D = A >> 4 vi. D = A >>> 4 vii. D = A << 4 viii. D = A <<< 4
2.21 Draw the hardware obtained if the following code is synthesized:
module reg3 (Q1,Q2,Q3,Q4, A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
always @(posedge CLK) begin
Q4 = Q3;
Q3 = Q2;
Q2 = Q1;
Q1 = A;
end endmodule
2.22 Draw the hardware obtained if the following code is synthesized:
module reg3 (Q1,Q2,Q3,Q4, A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
always @(posedge CLK) begin
Q1 = A;
Q2 = Q1;
Q3 = Q2;
Q4 = Q3;
end endmodule
2.23 Draw the hardware obtained if the following two modules are synthesized and describe the differences.
module reg3 (Q1,Q2,Q3,Q4,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
// first
always @(posedge CLK) begin
Q1 <= A;
Q2 <= Q1;
Q3 <= Q2;
Q4 <= Q3;
end endmodule
module reg3 (Q1,Q2,Q3,Q4,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
// first -> second always @(posedge CLK) begin
Q4 <= Q3;
Q3 <= Q2;
Q2 <= Q1;
Q1 <= A;
end endmodule
2.24 (a) Assume D150, D255, and D1 changes to 1 at time510 ns. What are the values of D1 and D2 after the following code has been executed once? Do the values of D1 and D2 swap?
always @ (D1) begin
D2 <= D1;
D1 <= D2;
End
(b) Assume D150, D255, and D1 changes to 1 at time510 ns. What are the values of D1 and D2 after the following code has been executed once? Do the values of D1 and D2 swap?
always @ (D1) begin
D2 = D1;
D1 = D2;
end
(c) How many latches will result when the following code is synthesized? Assume B is 3 bits long.
always @ (State) begin case(State) 2'b00: B = 5;
2'b01: B = 3;
2'b10: B = 0;
endcase end
Circle the correct choice:
i. 1 latch because 1 case is missing ii. 2 latches because state is 2 bits iii. 3 latches because B is 3 bits
iv. 5 latches because B is 3 bits and state is 2 bits v. None of the above. But it results in latches.
2.25 What is wrong with the following code for a half adder that must add if add signal equals 1?
always @(x) begin
if (add == 1) begin
sum = x ^ y;
carry = x & y;
end else begin
sum = 0;
carry = 0;
end end
(a) It will compile but will not simulate correctly.
(b) It will compile and simulate correctly but will not synthesize correctly.
(c) It will work correctly in simulation and in synthesis.
(d) It will not even compile.
2.26 For the following Verilog code, assume that D changes to 1 at time 5 ns. Give the values of A, B, C, D, E, and F each time a change occurs. That is, give the values at time 5 ns, 5 1 D, 5 1 2D, and so forth. Carry this out until 20 steps have occurred, until no further change occurs, or until a repetitive pattern emerges.
module prob(D);
inout D;
wire A, C;
reg B,E,F,temp_D;
initial begin
B = 1'b0;
E = 1'b0;
F = 1'b0;
temp_D = 1'b0;
end
assign C = A;
assign A = (B & !E) | D;
assign D = temp_D;
always @(A) begin
B = A;
end always begin wait(A)
E <= #5 B;
temp_D <= 1'b0;
F <= E;
end endmodule
2.27 Assuming B is driven by the simulator command:
force B 0 0, 1 10, 0 15, 1 20, 0 30, 1 35
Draw a timing diagram illustrating A, B, and C if the following concurrent state- ments are executed:
always @(B) begin A = #5 B;
end
assign #8 C = B;
2.28 Assuming B is driven by the simulator command:
force B 0 0, 1 4, 0 10, 1 15, 0 20, 1 30, 0 40
Draw a timing diagram illustrating A, B, and C if the following concurrent state- ments are executed:
always @(B) begin A <= #5 B;
end
assign #5 C <= B;
2.29 Assuming B is driven by the simulator command:
force B 0 0, 1 4, 0 10, 1 15, 0 20, 1 30, 0 40
Draw a timing diagram illustrating A, B, and C if the following statement is executed:
(a) always @(A,B) begin
#5 C <= A && B;
end
(b) always @(A,B) begin
#5 C = A && B;
end
(c) always @(A,B) begin
C <= #5 A && B;
end
(d) always @(A,B) begin
C = #5 A && B;
end
2.30 Given the following timing waveform for Y, draw D and E.
0 10 20 30 40 50
Y
D
E
10ns
10ns
5ns
2ns 3ns
wire #4 D; // net delay on wire D
assign #6 D = Y; // statement 1 2 inertial delay wire #6 E; // net delay on wire E
assign #4 E = Y; // statement 1 - inertial delay 2.31 Given the following timing waveform for Y, draw D and E.
0 10 20 30 40 50
Y
D
E
10ns
10ns
5ns
2ns 3ns
wire #3 D; // net delay on wire D
assign #5 D = Y; // statement 1 - inertial delay wire #5 E; // net delay on wire E
assign #3 E = Y; // statement 1 - inertial delay
2.32 In the following Verilog Code, A, B, C, and D are registers that are 0 at time 5 4 ns. If A changes to 1 at time 5 ns, make a table showing the values of A, B, C, and D as a function of time until time 5 18 ns. Include deltas. Indicate the times at which each process begins executing.
always @(A) begin
B <= #5 A;
C <= #2 B;
end always begin
wait(B);
A <= ~B;
D <= ~A ^ B;
end
2.33 If A 5 101, B 5 011, and C 5 010, what are the values of the following statements?
Assume A, B, and C are of reg type. Assume as many bits as necessary for the result.
(a) {A,B} | {B,C}
(b) A >> 2
(c) A >>> 2
(d) {A,(~B)} == 111110 (e) A | B & C
2.34 Consider the following Verilog code:
module Q3(A,B,C,F,Clk,E);
input A,B,C,F,Clk;
output reg E;
reg D,G;
initial begin
E = 1'b0;
D = 1'b0;
G = 1'b0;
end
always @(posedge Clk) begin
D <= A & B & C;
G <= ~A & ~B;
E <= D | G | F;
end endmodule
(a) Draw a block diagram for the circuit (no gates and at block level only).
(b) Give the circuit generated by the preceding code (at the gate level).
2.35 Implement the following Verilog code using these components: D flip-flops with clock enable, a multiplexer, an adder, and any necessary gates. Assume that Ad and Ora will never be 1 at the same time and enable the flip-flops only when Ad or Ora is 1.
module module1(A,B,Ad,Ora,clk,C);
input Ad,Ora,clk;
input [2:0]A,B;
output reg[2:0]C;
initial begin
C = 3'd0;
end
always @(posedge clk) begin
if(Ad == 1'b1) C <= A + B;
if(Ora == 1'b1) C <= A | B;
end endmodule
2.36 Draw the circuit represented by the following Verilog process:
always @(clk,clr) begin
if(clr == 1'b1) Q <= 1'b0;
else if(clk == 1'b0 && CE == 1'b1) begin
if(C == 1'b0) Q <= A & B;
else
Q <= A | B;
end end
Why is clr on the sensitivity list whereas C is not?
2.37 (a) Write a conditional signal assignment statement to represent the 4-to-1 MUX shown subsequently. Assume that there is an inherent delay in the MUX that causes the change in output to occur 10 ns after a change in input.
(b) Repeat (a) using an if-else statement.
(c) Repeat (a) using a case statement.
I0
I3 I2 I1 A9
B B9 0
C D F
2.38 (a) Write at least two different Verilog modules that are equivalent to the following pseudo code:
A = B1 when C = 1 else B2 when C = 2 else B3 when C = 3 else 0;
(b) Draw a circuit to implement the following statement,
A = B1 when C1 = 1 else B2 when C2 = 1 else B3 when C3 = 1 else 0;
2.39 Write a Verilog description of an SR latch.
(a) Use a conditional assignment statement (i.e., a behavioral description).
(b) Use the characteristic equation in the Verilog description.
(c) Use the logic gate level structure of an SR latch in the model.