Introduction to Programmable Logic Devices
3.4 Field-Programmable Gate Arrays (FPGAs)
3.4.2 FPgA Programming Technologies
Sea-of-Gates Architecture
The sea-of-gates architecture is yet another manner to organize the logic blocks and interconnect in an FPGA. The general FPGA fabric consists of a large number of gates, and then there is an interconnect superimposed on the sea of gates as illus- trated in Figure 3-27(d). Plessey, a manufacturer that was in the FPGA market in the mid-1990s, made FPGAs of this architecture. The basic cell used was a NAND gate, in contrast to the larger basic cells used by manufacturers such as Xilinx. While the terminology sea of gates is the most popular, there are also the terminologies sea of cells and sea of tiles to indicate the topology of FPGAs with a large number of fine-grain logic cells. The Microsemi Fusion FPGAs contain a sea of tiles, where each tile can be configured as a 3-input logic function or a flip-flop/latch.
P Q R S
X
M M=SRAM cell
(a) Pass transistor connecting two points
(b) Multiplexer controlled by two memory cells Routing
wire
To logic cell input Routing
wire
A B
M
Routing wire
M
An SRAM cell usually takes six transistors, as illustrated in Figure 3-29. Four cross-coupled transistors are required to create a latch, and two additional tran- sistors are used to control passing data bits into the latch. When the Word Line is set to high, the values on the Bit Line will be latched into the cell. This is the write operation. The read operation is performed by precharging the Bit Line and Bit Line9 to a logic 1 and then setting Word Line to high. The contents stored in the cell will then appear on the Bit Line. Some SRAM cell implementations use only five transistors. One advantage of using static RAM is that it is volatile and you can write new contents again and again. This provides flexibility during prototyping and development. Another advantage is that the fabrication steps for making SRAM cells are not different from the steps for making logic. The major disadvantage of the SRAM programming technology is that five or six transistors are used for every SRAM cell. This adds a tremendous cost to the chip. For example, if an FPGA has 1 million programmable points, it means that approximately 5 or 6 million transis- tors are employed in achieving this programmability.
Q5 Q2
Q1 Q3
Q4
Q6 Bit line
gnd Word line
Vdd
Bit line
Being volatile can become a disadvantage when an FPGA is used in the final product. Hence, when SRAM FPGAs are used, a nonvolatile device such as an FIgure 3-28: Routing
with Static RAM Programming
FIgure 3-29: Typical 6-Transistor SRAM Cell
EPROM should be used to permanently store the configuration bits. Typically, what is done is to use the EPROM as a “boot ROM,” The EPROM contents are transferred to the SRAM when power comes up.
Xilinx FPGAs were the first FPGAs to use SRAM as the programming tech- nology. In fact, it is the flexibility and reprogrammability of SRAM FPGAs that caused FPGAs to become widely popular. Now, many companies use the SRAM programming technology for their FPGAs.
EPROM/EEPROM Programming Technology
In the EPROM/EEPROM programming technology, EPROM cells are used to control programmable connections. Assume that EPROM/EEPROM cells are used instead of the SRAM cells in Figure 3-28. A transistor with two gates—a floating gate and a control gate—is used to create an EPROM cell. Figure 3-30 illustrates an EPROM cell. The pull-up resistor connects the drain of the tran- sistor to the power supply (labeled VDD in the figure). To turn the transistor off, charge can be injected on the floating gate using a high voltage between the control gate and the drain of the transistor. This charge increases the threshold voltage of the transistor and turns it off. The charge can be removed by exposing the floating gate to ultraviolet light. This lowers the threshold voltage of the transistor and makes it function normally.
EPROM transistor Pull-up resistor
gnd Floating gate
Control gate Bit line
Word line
VDD
EPROMs are slower than SRAM; hence, SRAM-based FPGAs can be pro- grammed faster. EPROMs also require more processing steps than SRAM.
EPROM-based switches have high ON resistance and high static power consump- tion. The EEPROM is similar to EPROM, but removal of the gate charge can be done electrically.
Flash memory is a form of EEPROM that allows multiple locations to be erased in one operation. Flash memory stores information in floating gate transistors as FIgure 3-30: The EPROM
Programming Technology
in traditional EPROM. The floating gate is isolated by an insulating oxide layer;
hence, any electrons placed there are trapped. The cell is read by placing a specific voltage on the control gate. When the voltage to read is placed, electrical current will or will not flow depending on the threshold voltage of the cell, which is con- trolled by the number of electrons trapped in the floating gate. In some devices, the information is stored as absence or presence of current. In some advanced devices, the amount of current flow is sensed; hence, multiple bits of information can be stored in a cell. To erase, a large voltage differential is placed between the control gate and the source, which pulls electrons off. Flash memory is erased in segments/
sectors; all cells in a block are erased at the same time.
The Antifuse Programming Technology
In some FPGAs, the programmable connections between different points are achieved by what is called an “antifuse.” Contrary to fuse wires that blow open when high current passes through them, the “antifuse” programming element changes from high resistance (open) to low resistance (closed) when a high voltage is applied to it. Antifuses are often built using dielectric layers between N1 diffusion and poly- silicon layers or by amorphous silicon between metal layers. Antifuses are normally OFF; permanently connected links are created when they are programmed. The process is irreversible; hence, antifuse FPGAs are only one-time programmable.
Programming an antifuse requires applying a high voltage and currents in excess of normal currents. Special programming transistors larger than normal transistors are incorporated into the device in order to accomplish the programming. There are various antifuse technologies; a popular one is the Via antifuse technology.
Antifuse technology has the advantage that the area consumed by the program- mable switch is small. Another advantage is that antifuse-based connections are faster than SRAM- and EEPROM-based switches. The disadvantage of the antifuse technology is that it is not reprogrammable. It is a permanent connection; if an error or design change necessitates reprogramming, a new device is required.
Comparison of Programming Technologies
Table 3-8 compares the characteristics of the major programming technologies used by FPGAs. Only the SRAM and EEPROM programming technologies allow in-circuit programmability. In-circuit programmability means that an FPGA
Programming Technology
Volatile/
Nonvolatile reprogrammable
Area
Overhead resistance Capacitance
SrAM Volatile In-circuit
reprogrammable Large Medium-high High
ePrOM Nonvolatile Out-of-circuit repro- grammable
Small High High
eePrOM/Flash Nonvolatile In-circuit
reprogrammable Medium to high High High
Antifuse Nonvolatile Not reprogrammable Small Small Small
TABLe 3-8: Characteristics of the Major FPGA Programming Technologies
can be reprogrammed without removing it from the board in which it is used.
In-circuit programmability is not possible in traditional EPROM-based devices, but EEPROM and flash technologies allow in-circuit reprogrammability.
SRAM FPGAs have several disadvantages: high area overhead, large delays, volatility, and others. However, the in-circuit programmability and fast program- mability have made them very popular. SRAM FPGAs are more expensive than other types of FPGAs because each programmable point uses six transistors.
This extra hardware contributes only to the reprogrammability but not to the actual circuitry realized with the FPGA. EEPROM- and Flash-based FPGAs are comparable to SRAM FPGAs in many respects; however, they are not as fast as SRAM FPGAs.