Introduction to Programmable Logic Devices
3.4 Field-Programmable Gate Arrays (FPGAs)
3.4.1 Organization of FPgAs
Figure 3-26 shows the layout of a typical FPGA. The interior of FPGAs typically contains three elements that are programmable:
Programmable logic blocks
Programmable input/output blocks Programmable routing resources
Programmable Logic Block
Programmable I/O Block
Programmable Interconnect Area
Arrays of programmable logic blocks are distributed within the FPGA. These logic blocks are surrounded by input/output (I/O) interface blocks. These I/O blocks can be considered to be on the periphery of the chip. They connect the logic signals to FPGA pins. The space between the logic blocks is used to route connec- tions between the logic blocks.
FIgure 3-26: Layout of a Typical FPGA
The “field” programmability in FPGAs is achieved by reconfigurable elements, which can be programmed or reconfigured by the user. As mentioned, there are three major programmable elements in FPGAs: the logic block, the interconnect, and the input/output block. Programmable logic blocks are created by using multi- plexers, look-up tables, and AND-OR or NAND-NAND arrays. “Programming”
them means changing the input or control signals to the multiplexers, changing the look-up table contents, or selecting or not selecting particular gates in AND-OR gate blocks. For a programmable interconnect, “programming” means making or breaking specific connections. This is required to interconnect various blocks in the chip and to connect specific I/O pins to specific logic blocks. Programmable I/O blocks denote blocks that can be programmed to be input, output, or bidirec- tional lines. Typically, they can also be “programmed” to adjust the properties of their buffers such as inverting/non-inverting, tristate, passive pull-up, or even to adjust the slew rate, which is the rate of change of signals on that pin.
What makes an FPGA distinct from a CPLD is the flexible general-purpose interconnect. In a CPLD, the interconnect is fairly restricted. The general- purpose interconnect in an FPGA gives it a lot of flexibility, but it also has the dis- advantage of being slow. A connection from one part of the chip to another part might have to travel through several programmable interconnect points, resulting in large and unpredictable signal delays.
Although Figure 3-26 was used to illustrate the general structure of an FPGA, not all FPGAs look like that. Commercial FPGAs use a variety of architectures.
The FPGA architecture or organization refers to the manner or topology in which the logic blocks and interconnect resources are distributed inside the FPGA. The organization that is presented in Figure 3-26 is often referred to as symmetrical array architecture. If one examines the various FPGAs that have been on the mar- ket since their inception in the late 1980s, one could classify them into four different basic architectures or topologies:
Matrix-based (symmetrical array) architectures Row-based architectures
Hierarchical PLD architectures Sea-of-gates architecture
These architectures are illustrated in Figure 3-27. This classification is based on the layout of the general purpose logic region in the FPGAs. Modern FPGAs contain special-purpose blocks including a microprocessor, and the special-purpose blocks are usually embedded into the center or on the peripheries.
Matrix-Based (Symmetrical Array) Architectures
The logic blocks in this type of FPGA are organized in a matrix-like fashion, as illustrated in Figure 3-27(a). Most Xilinx FPGAs belong to this category. The logic blocks in these architectures are typically of a large granularity (capable of implementing 4-variable functions or more). These architectures typically contain 8 3 8 arrays in the smaller chips and 100 3 100 or larger arrays in the bigger chips.
The routing resources are interspersed between the logic blocks. The routing in these architectures is often called two-dimensional channeled routing since routing resources are generally available in horizontal and vertical directions.
(a) Matrix based (symmetrical array) Interconnect
Logic block
(d) Sea of gates
Logic block
Interconnect overlayed on logic blocks (b) Row based
Interconnect
Logic block
Group of logic
blocks (with local interconnect)
Global inter- connect
(c) Hierarchical
Local InterconnectLocal Interconnect Local InterconnectLocal Interconnect
Row-Based Architectures
These architectures were inspired by traditional gate arrays. The logic blocks in this architecture are organized into rows as illustrated in Figure 3-27(b). Thus, there are rows of logic blocks and routing resources. The routing resources interspersed between the rows can be used to interconnect the various logic blocks. Traditional mask-programmable gate arrays use very similar architectures. The routing in these architectures is often called one-dimensional channeled routing, because the rout- ing resources are located as a channel in between rows of logic resources. Some Microsemi FPGAs employ this architecture.
Hierarchical Architectures
In some FPGAs, blocks of logic cells are grouped together by a local interconnect, and several such groups are interconnected by another level of interconnect. For instance, in Altera APEX20 and APEX II FPGAs, 10 or so logic elements are connected to form what Altera calls a Logic Array Block (LAB), and then sev- eral LABs are connected to form a MEGALAB. Thus, there is a hierarchy in the organization of these FPGAs. These FPGAs contain clusters of logic blocks with localized resources for interconnection. The global interconnect network is used for the interconnections between the clusters of logic blocks in these FPGAs.
FIgure 3-27: Typical Architectures for FPGAs
Sea-of-Gates Architecture
The sea-of-gates architecture is yet another manner to organize the logic blocks and interconnect in an FPGA. The general FPGA fabric consists of a large number of gates, and then there is an interconnect superimposed on the sea of gates as illus- trated in Figure 3-27(d). Plessey, a manufacturer that was in the FPGA market in the mid-1990s, made FPGAs of this architecture. The basic cell used was a NAND gate, in contrast to the larger basic cells used by manufacturers such as Xilinx. While the terminology sea of gates is the most popular, there are also the terminologies sea of cells and sea of tiles to indicate the topology of FPGAs with a large number of fine-grain logic cells. The Microsemi Fusion FPGAs contain a sea of tiles, where each tile can be configured as a 3-input logic function or a flip-flop/latch.