As design complexity increases, the limitation of this approach becomes more apparent. The design is divided into successive levels of sub-systems until each one has a manageable complexity - the hierarchical design method [27].
Interplay of Space and Time
By dividing the design into these levels, the designer only needs to focus on one level at a time.
Notation for Describing VLSI Systems
Therefore, the specification language must have a formal semantics so that the specification of a given design can be formally verified. With explicit time as a parameter, change of state can be expressed by state transition functions in the manner of [1].
An Overview
Therefore the language is history sensitive and at the same time allows clarity of functional programming. The same note applies to systems ranging from the level of transistors to the level of communication processes.
Model of Computation
The process now starts an operation, called i'th call, which consists of 1) emptying the selected input ports and 2) evaluating the state transition function (Ring a transition as in Petri net), called the tenth call of the process where t is the time coordinate of the process. If some of the designated output ports are not emptied, the process waits until they are emptied and then fills them.
Universality of the Model
After that in the data store (the symbol in the corresponding square in Τ') and input go (the current state in Τ') are applied to the state transition function (Rnite state machine in Τ'), the process is updating the data store with the new symbol ½ι (as Τ' would write on the tape), sends qι (the new state of Τ') to the left, right, or "self-connected" output ports according to the direction of the readhead movement in Τ'. Machine O either continues indefinitely as machine T would or terminates after a ßnite number of events and the result of the computation is the symbols in the data store in each process.
The Language CRYSTAL *
These functions are primitives of the language and should not be confused with those of the system under construction. At the beginning of the calculation, only the initial state and the initial input are determined.
The Syntax of CRYSTAL
The Semantics of CRYSTAL
The Behavior of an Algorithm
The semantics of (BEHAVIOR OF STA) is an n' tuple function from P"*' to P"∖ Thus, the system described by the algorithm can be abstracted as a system of state transition functions mapping inputs and current states (Xi, . ., -X^∏γ) to outputs and subsequent states (T^,.., X∏') - It can therefore serve as a primitive building block ((COMPOSITE STF)) for constructing a more complex system.
A Simple Example of a Space- Time Algorithm
The behavior of the algorithm is λa.f⅛c(i<,te<κfy) == λa.a!, and thus the algorithm implements the factorial function correctly. In the following, a formal description of the matrix multiplication algorithm is given by [22] with a proof of accuracy.
The same algorithm with a different timing scheme, e.g., a self-timing scheme [39] can conceptually simplify process interaction, data mode, and system initialization. On the other hand, the self-timed scheme does not have any global control, the ordering of system events is an emergent property of local synchronization.
A Synchronous System
The resulting space-time agorithm is a system of recursion equations in a<,ut, b.ut and <⅛ut and initial inputs ao(z,y,z), bo(z, y, z) and co(z, y, z). The above algorithm is defined given the initial inputs ao, bo and co. In order to see that the above algorithm performs matrix multiplication, it is necessary to map the elements of the matrices from indices to spatiotemporal coordinates (input mapping function). and mapping the final output from space-time coordinates to a matrix structure (output mapping function). The above system of recursion equations and input-output mapping functions must be shown to correctly implement the known identity and matrix functions, viz.
Given any point in the space-time domain, this function gives the values computed by the algorithm given the initial inputs ao, bo, and co-.
A Self-timed System
To obtain the semantics of the aigorithm, the semantics of these free variables must first be obtained. From both algorithms, we observe that the input and output mapping functions and the behavioral description of the hexagonal array are much simpler for the self-timed version. The simplicity of the self-time version is a reward of the more sophisticated synchronization method.
A function to map the output from a spatiotemporal structure to a value domain structure.
Pipelined Architecture
F⅛from the functional description of shift registers (4), (5) and (6) it is possible to derive a functional description of the internal state of bb. The multiplication of two n-bit binary numbers can be represented by repeating the partial product. We approach this proof differently than for the systolic arrays in the previous sections, where we obtain a solution with the space-time domain and .
In this proof, the spacetime coordinates are mapped to the coordinates that indicate the stage of the partia.
Circuit Components as Processes
In this way, a VLSI system can be described and verified hierarchically in a simple and uniform way all the way from networks of transistors to high-level networks of processors.
Data Types for Transistor Networks
Primitives — MOS Switch Level Model
The equivalent admittances from the Î sources or stored charge and the Ô sources or stored charge are then calculated separately, treating the transistors with x at their gates as on. Once all three admittances are evaluated, they are combined to produce the new node power and voltage. Formal parameters are used when designing functions and should not be confused with states if the same symbols are used.
The inputs and outputs are not explicitly distinguished from the states in which a process is defined, although this information is in the higher-level description where the process is used.
Transistor as a Process
Node as a Process
For transistors with X on their gate, we get a zero part and a one part assuming maximum conductance. Since the equivalent admittance a must come from Î or Ô, at !east one of y and z at !east must be as large as a. If one of y and z is less than a, we can be sure that the larger results from the dominant admittance path, even if all transistors with X at their gates are treated as off.
On the other hand, if both y and z are as large as or greater than a, we cannot be sure that there will not be an equal strength path to both 1 and 0 for some on or off choice for transistors with X on their gates.
The state transition function that relates outputs and next state to inputs and current state is the fixed point of the recursion equations describing the network. The following are the recurring ones. equations for calculating the equivalent access at each node for an arbitrary conduction network. This equation determines the equivalent access for each node in terms of the equivalent access of ai.
The equations are similar to those above, except that the maximum conductance G2 is used instead of Gj, and the equivalent admittance A obtained above is used.
Transistor Network as a Process
There are two possible extreme network topologies; one is given by the assumption of maximum conductance and the other by the assumption of minimum conductance. We further λ-subtract the appropriate arguments to obtain the following function that models the behavior of a transistor network.
Functional Abstraction and Semantic Hierarchy
Data Abstraction
It follows that any provably correct simulation technique will be one of two types: i) The entire design is represented as an implementation with objects that are abstract models of the medium at a lower level (eg, a transistor model). A representation of a simulation operation that is a direct image of a fully instantiated implementation in the medium. ii). Each implementation level consists of objects that are abstract models of the implementation at the level below it.
The second approach allows the implementation details to be hidden, thus providing a clearer conceptualization of the design and a more efficient simulation.
Multi-level and Mixed-level Simulation
A multi-level simulator, when used as a tool to verify a hierarchical design, must provide a way to ensure the consistency of the design through all levels. On the other hand, the simulator must allow blocks from different levels to be connected through proper interfaces that handle the timing and matching of different input/output data types. In this chapter we present a simulator in which a uniform representation is used at all levels of the design.
An abstraction method is described for maintaining consistency between levels and proper interrelation of time and data types.
Semantic Hierarchy and Syntactic Hierarchy
Since each of a gate-level cell's input nodes is the gate node of a transistor, the cell will see no intermediate state at that node until the node reaches the inner-conductance-level stable state described above. The gate level abstraction is at a lower level than the clocked cell level, since not only is the stable state at the transistor level preserved, but all the stable states at the conduction level are also preserved. Bryant [3] points out that the gate level cells provide a useful modeling abstraction as there is no need to keep track of the a⅛naf 4trenpi⅛ used at the conductance level.
Note that an IPB cell is a syntactic cell, and therefore each of the three subcells is called only once.
THEN
- Implementation of the Simulator
- Summary
- Summary of the Thesis
- Extension to Nondeterministic Systems
- Future Work
A function that maps inputs in a high-level data representation to lower-level inputs. ii) Implementation at a lower level. iii). The cell contains a specification of its components, i.e. implementation elements of lower-level cells, and the procedure for calculating its result. In an object-oriented view of computing such as Simula [2], Smalltalk [18], etc., the above templates are superclasses of user-defined classes (cells).
A clear distinction is made between the modularization for ease of specification and for semantic abstraction – the syntactic hierarchy and the semantic hierarchy, respectively.
