0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VGS (V)
0 5 10 15 20 25 30 35 40
g m/I D (1/V)
0 5 10 15 20 25 30 35 40
I D/W(A/m)
NMOS PMOS NMOS PMOS
Figure 3.10: Transconductance-drain current ratio(gIm
D) and normalized current (IWD) curves of nMOS and pMOS devices (VDS = 0.5 V andW = 10µm, andL= 1µm).
W5= 2.ID1,2 ID/W
5
(3.36)
Step :5 The bias current in M6,7 is equal to B.ID1,2 and the width of M6 and M7 is given by W6,7= B.ID1,2
ID/W
3,4
(3.37)
Step :6 Similarly, the bias current in M8,9 also equal to B.ID1,2 and the size of M8 andM9 is given by W8,9= B.ID1,2
ID/W
8,9
(3.38)
3.7 Extraction of Design Parameters with STI Effect
Table 3.1: Design specifications of two-stage OTA
Specification Value
VDD(V) 0.5
CL (pF) 2
DC-gain :AV (dB) >40
Gain-bandwidth: fu (MHz) 4
Phase margin: φM (deg) 60
Slew rate: (V /µs) 2
Input common-mode range: ICMR (V) 0.25−0.3
Table 3.2: Design parameters of two-stage OTA for the specifications given in Table. 3.1.
Parameter Value Units CC 0.44 pF W1 140 µm W2 140 µm W3 18.5 µm W4 18.5 µm W5 16.5 µm W6 200 µm
W7 70 µm
performance and does not meet its specifications.
Traditionally, theNF will be obtained by dividing the total width by the maximum allowable WF. This procedure works well for the long-channel CMOS devices due to negligible STI effect. For small- channel CMOS devices with STI effect, the conventional method for finding the WF is by tweaking the width of each MOSFET until the circuit meets the specifications. This is a difficult and time consuming process. Moreover, as the transistor count increases in a circuit, the process becomes more complicated. To overcome these constraints, we proposed a new design procedure. In which, the geometry of MOSFET is resized by plotting the normalized current characteristics (i.e., ID/W) using each design parameter for different values of NF. The normalized current characteristics for different NF is shown in Fig. 3.11, whereas the device dimensions assumed as W = 20 µmand L= 0.2 µm.
As discussed, the gm/ID characteristics are less affected due change in NF. Therefore, the new geometries of each design parameter is evaluated using gm/ID and ID/W characteristics. Before evaluation of new geometries, the minimum NF for each design parameter need to be calculated from maximum available finger width of CMOS process. And, the new device geometry is calculated for the respective NF usingID/W characteristics. The step-by-step procedure for resizing of design
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VGS (V)
0 25 50 75 100 125 150 175 200 225
ID/W (A/m)
NF=2 NF=5 NF=10 NF=20 NF=40
0.2 0.25 0.3 VGS (V) 0
0.25 0.5
0.5 0.55 0.6 VGS (V) 10
20 30 40
Figure 3.11: Normalized current ID/W characteristics of multifinger MOSFET (W = 20 µm, L= 0.2 µm, VDS = 0.5 V).
parameters with STI effect is described as follows:
Step 1: The minimumNF of each transistor is calculated using total device width (W) of transistor and maximum allowable finger width (WF,max). In UMC 65-nm CMOS process theWF,max = 10µm.
If the device width is greater than WF,max, then the device is represented as multifinger device.
If any fractional value appears duringNF calculations, which is approximated to the next integer value because NF should be a integer number. The expression of NF is given by
NF =
WK WF,max
(3.39) where WK represents width ofKth transistor
Example: From Table 3.2, the transistorM5 should represented as multiple finger, sinceW5 = 16.5 µm which is greater than 10 µm and NF of M5 is equal to 2. Similarly, the NF will be calculated each transistor.
Step 2: In direct scaling, the finger widthWF is calculated for theNF (obtained from Step 1).
WF = WK
NF (3.40)
Example: TheW ofM transistor is 8.25 µm
3.7 Extraction of Design Parameters with STI Effect
Step 3: As discussed in Section 3.2, the MOSFET characteristics get affected due to STI effect (i.e., change inNF). Hence, it is necessary to re-size multifinger devices by considering the STI effect.
In proposed method, the ID/W characteristics of each transistor is extracted like in Fig. 3.11 for NF (obtained from step 1) and the new geometries for two-stage OTA computed using the following relation:
(WK)NF = IDK hID/W
K
i
NF
(3.41)
where, (WK)NF is width of Kth MOSFET with consideration of NF, IDK is drain current of Kth transistor,h
ID/W
K
i
NF is normalized current of Kth device for NF (obtained from step 1)
Note: The bias conditions of each transistors remain same as before (i.e., VGS, ID calculated using design procedure in Section 3.4 for a given specification in Table 3.1).
Example: The width ofM5 calculated for required NF (obtained from Step 1) is 13.5 µm.
Step 4: The finger width of multifinger device for requiredNF is given by
(WF)NF = (WK)NF
NF (3.42)
where (WF)NF is finger width obtained for requiredNF Example: The (WF)NF of M5 transistor is 6.75 µm
In order to show the STI effect of multifinger MOSEET on circuits performance, in this work, we considered three different cases such as T1, T2 and T3. The WF,max for T1, T2 and T3 is assumed as 10 µm, 5 µm and 2.5 µm, respectively.
By following the steps 1-4 mentioned above, for different test cases the designed parameters are resized. The design parameters for different test cases, using direct scaling and proposed method are listed in Table 3.3. It is clear from Table 3.3 that as compared to the direct scaling, the device finger width for the proposed method is less under the same biasing condition. For example, the transistors W1 andW2 in Fig. 3.3, require 14 fingers with each finger width of 10µmusing direct scaling whereas using the proposed design the width of each finger is only 5.3 µm for same number of fingers.
signofAnalogCircuitswithSTIEffect
Table 3.3: Design parameters of two-stage OTA with STI effect and direct scaling
Design Width (µm) T1(WF,max= 10µm) T2(WF,max= 5µm) T3(WF,max= 2.5µm) Parameter NF = 1 NF WF(µm) (WF)NF (µm) NF WF(µm) (WF)NF(µm) NF WF(µm) (WF)NF(µm)
W1,2 140 14 10 5.3 28 5 2.66 56 2.5 1.45
W3,4 18.5 2 9.25 8.75 4 4.6 4.25 8 2.3 2
W5 16.5 2 8.25 6.75 4 4.1 3 8 2 1.45
W6 200 20 10 8.75 40 5 4.25 80 2.5 2
W7 70 7 10 6.3 14 5 3 28 2.5 1.5
NF: Number of Fingers; WF: Finger width obtained from direct scaling; (WF)N
F: Finger width obtained for requiredNF.
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3.7 Extraction of Design Parameters with STI Effect
The design parameters of bulk-driven current mirror OTA are calculated using the step by step procedure outlined in Section 3.5 and are tabulated in Table 3.4. The design parameters of bulk-driven OTA are summarized in Table 3.5. In Table 3.5, the channel length of M1,2 devices is 0.5 µm and other devices is 1 µm.
Table 3.4: Design specifications for bulk-driven current mirror OTA
Specification Value
VDD(V) 0.5
CL (pF) 10
DC-gain :AV (dB) >15 Gain-bandwidth: fu (kHz) 100 Phase margin: φM (deg) 60
Table 3.5: Design parameters of bulk-driven OTA for the specifications given in Table. 3.4.
Parameter Value Units W1 55.6 µm W2 55.6 µm W3 7.1 µm W4 7.1 µm W5 63.4 µm W6 188 µm W7 188 µm W8 879 µm W9 879 µm
By following the Steps 1-4 mentioned above, the designed parameters of bulk-driven OTA are resized for different test cases. The design parameters for different test cases, using direct scaling and proposed method are tabulated in Table 3.6.
signofAnalogCircuitswithSTIEffect
Table 3.6: Design parameters of bulk-driven OTA with STI effect and direct scaling
Design Width (µm) T1(WF,max= 10µm) T2(WF,max= 5µm) T3(WF,max= 2.5µm) Parameter NF = 1 NF WF(µm) (WF)NF (µm) NF WF(µm) (WF)NF(µm) NF WF(µm) (WF)NF(µm)
W1,2 55.6 6 9.26 8.2 12 4.63 4 24 2.31 2
W3,4 7.1 1 7.1 7.1 2 3.55 3.25 4 1.77 1.65
W5 63.4 7 9.01 8.39 14 4.52 4.17 28 2.26 2.1
W6,7 188 19 9.89 6.6 38 4.95 3.56 76 2.47 2
W8,9 879 88 9.98 9 176 5 4.52 352 2.49 2.29
NF: Number of Fingers; WF: Finger width obtained from direct scaling; (WF)N
F: Finger width obtained for requiredNF.
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