1.1 Introduction
In recent years, the demand for emerging battery-operated portable and wearable electronics de- vices such as mobile phones, music players, and biomedical instruments (hearing aids, implantable cardiac pacemakers and heart-rate detectors) has been increasing. Most of these applications use system-on-chip (SoC) that consists of analog, digital, and intrinsic mixed-signal circuits. In order to extend the battery life in these systems, their SoC design should be more power efficient. The interaction among the different factors heading to the continuous growth of electronic devices can be better understood with the aid of Fig. 1.1. Note that behind the progress of integrated circuits, there is always a driving factor dictated by technology limitations and a driving factor related to market demand.
Low-Power
Low-Voltage Portability
Integration
Market Technology
new-possibilities new-solutions
demand
price scaling
scaling peformance
battery life
digital heat-dissipation
Figure 1.1: Factors driving the low-power and low-voltage trend [1]
The increasing demand for portable systems such as computers, digital communication systems and consumer electronics poses new challenges before the semiconductor industry. The driving force for this trend is the ability of the industry to produce faster and more power-efficient circuits, which is mainly due to the continuous scaling of the CMOS technology. The evolution in CMOS technology is motivated by decreasing price-per-performance for digital circuitry [3]. The continuous scaling of the MOSFET channel length (L) increases the maximum number of transistors per unit area. According to Moore’s law, the amount of components per chip doubles every 24 months [1]. The speed of integrated circuits and more electronic functions per unit area has increased as a result of miniaturization and at the same time the maximum allowable supply voltage (VDD) has decreased. Hence, a relatively large threshold voltage (VT H) needs to be maintained to limit the OFF current in transistors.
The CMOS technology offers the unique possibility of integration of both analog and digital circuits
on the same chip. The low-supply voltage is especially beneficial to digital integrated CMOS circuits, since their power consumption is proportional to the square of the supply voltage, i.e., reducing the supply voltage to half will reduce the power consumption to a quarter from its original value. In analog signal processing the power consumption is not directly related to the supply voltage but, instead, it is basically set by the required signal-to-noise ratio (SNR) and the frequency of operation (or the required bandwidth).
The analog circuits employed in applications such as wireless sensor networks, wearable battery powered systems, and implantable circuits for biological applications need to consume very low amount of power such that the entire system can survive for a very long time without the need for changing or recharging battery. Using new power supply techniques such as energy harvesting and printable batteries, is another reason for reducing power dissipation.
1.1.1 Motivation
The current scope of this research is motivated by the implementation of analog circuits with chal- lenges imposed by sub-nanometer CMOS technologies. This work is to develop low-power operational transconductance amplifiers (OTAs) for low-voltage applications. Since, OTA is a basic building block in analog and mixed-signal circuits such as analog filters, ADC/DAC converters, low-dropout regu- lators (LDOs), sample and hold circuits, references circuits and buffer amplifiers. The analog and mixed-signal circuits may require multiple OTAs, where the power consumption of individual OTA is critical in order to prolong the battery life. Hence optimizing the performance of individual compo- nents while keeping the power consumption low is critical to build an overall energy efficient system.
Therefore, one must design an OTA to operate with as low a power as possible while maintaining an acceptable noise performance and linearity requirement. One of the most important features in low- voltage amplifier designs is ensuring that the amplifier maintains constant behaviour in the presence of rail-to-rail input common-mode variations while providing a rail-to-rail output to maximize SNR.
Therefore, an efficient input stage for low-voltage operation is essential while designing OTA.
The conventional analog circuits are mainly based on gate-driven differential transistor pairs, where the input signal modulates the gate voltage of input devices. This approach is unsuitable for low supply voltage due to the Vth limitation in signal path. The input devices operate in the conductance region only for input common-mode level toward positive or negative supply rail. The input common-mode range of gate-driven circuits can be extended with the help of complementary input differential stage
1.1 Introduction
or dynamic level shifter. But these circuits require complex biasing circuits to minimize the dead zone in the input range.
In recent years, various low-voltage design techniques such as bulk-driven, floating-gate, self- cascode and low−VthMOSFETs have been developed, which are capable of reducing the power supply requirements [4, 5]. Among these, the bulk-driven MOSFET is one of the most promising technique for design of analog circuits in low-voltage environment. Here, the input signal drives bulk-terminal of the input MOSFET devices while a sufficient gate voltage keeps the input devices in conducting region even for rail-to-rail input common-mode range. This approach eliminates Vth requirement in input signal path, thereby pushing the minimum operational supply voltage to its limit. However, the bulk-driven devices have few disadvantages like, low transconductance, increased area, and large input capacitance from its well structure. The bulk-transconductance (gmb) of bulk-driven MOSFET is considerably smaller (2-5 times) than that of gate transconductance (gm), which affects the gain, input noise and frequency response of the OTA. In addition, the drive strength of bulk-driven devices is very poor as compared to the gate-input counterparts.
For the aforementioned reasons, in this thesis, the performance degradation issues in low-voltage bulk-driven OTAs are addressed along the following directions.
• Improving the speed (i.e., gain-bandwidth (GBW)) of bulk-driven circuits under low-voltage environment.
• In low-voltage operation, boosting the gain is more difficult due to the absence of the transistor cascoding, and will cost more area and power consumption.
• The low-voltage circuits has to provide rail-to-rail output swing in order to maximize the SNR.
In addition, the amplifier should maintain the constant behaviour in the presence of process, voltage and temperature (PVT) and input common-mode voltage variation while providing a rail-to-rail output.
• Improving the driving capability of bulk-driven OTAs under low-voltage environment.
1.1.2 Problem formulation
OTA is one of the most important building blocks of analog and mixed-mode systems. The bulk- driven transistors are normally used for designing an OTA with rail-to-rail operating range. However,
bulk-driven devices have certain limitations as mentioned in the previous Section. 1.1.1. In order to overcome these limitations, in this thesis, we proposed several techniques. The goal of this thesis is to develop power-efficient bulk-driven OTAs for low-voltage applications. To meet this goal the following specific contributions are attempted in this thesis.
• A systematic design procedure is suggested to minimize the variation of circuit performance due to layout dependent effects.
• Investigation of high DC-gain bulk-driven OTA topology for low-voltage and low-power appli- cations.
• An ultra-low-voltage bulk-driven with rail-to-rail input/output swing is investigated for low- frequency applications.
• An adaptive biasing and slew rate enhancer techniques are suggested for improving the driving capability of low-voltage bulk-driven OTAs.
The scaling of power consumption is proportional to that of operating frequency of OTA. The tuning of operating frequency with required specifications is the main objective of this work. Overall, this thesis is aimed at improving the performance of bulk-driven OTAs under low-voltage environment.
The intended capabilities and advantages of the suggested techniques are verified through post-layout simulations.