4.1 Introduction
4.1 Introduction
The design of high performance with low-power analog circuits is becoming increasingly challenging with the sub-micron CMOS technology. OTA is an important building block in analog circuits and the efficient design of OTA will lead to greater enhancement in the overall analog circuit performance.
Design of a high-gain OTA with low-voltage supply is a challenging task, since the conventional cascoding technique is not suitable for OTA with low-voltage supply, due to limitation on signal swing. The OTA should provide high gain to ensure the closed loop transfer function independent of the overall forward path gain, when used in the negative feedback loop. One essential challenge in high resolution and high speed OTA design is simultaneous increase of gain and unity gain frequency.
To accomplish these requirements, it is necessary to develop new design techniques to improve the gain with low-voltage supply without loss of performance.
This chapter discusses a PVT-intensive pseudo-differential bulk-driven OTA operating in weak inversion region suitable for low-voltage applications. The proposed bulk-driven OTA offers high DC-gain and high GBW. The amplifier uses a bulk-driven input for rail-to-rail input operation and a differential Class-AB output stage for rail-to-rail output swing. The proposed design employs a partial positive feedback technique for increasing the low-frequency gain of the bulk-driven OTA. In addition, a cross-forward (CF) stage is used to further improve the driving capability and DC-gain. Moreover, the proposed design performance is insensitive to PVT variation..
ow-VoltagePVT-InsensitiveBulk-DrivenOTAwithEnhancedDC-gain
Vdd
VBN
V1P V1N
ViN ViP
V1P V1P
V1N V1N
VOP VON
VCMF VCMF
VBP VBP
VON VOP
VCMF
VREF
Input Stage Output Stage CMFB
M2A
M1B M4A
M2B
M4B
M3A M3B
M1A M5A M5B
M6A M6B
M7A M7B
M8A M8B
MC1
CC CC
MC2
MC3 MC4
MC5
Cross forward stage
VFN VFP
Vdd
IB
MT2
MT1
MT3
MT4
MT5
VBN VBP
Bias Stage
Figure 4.1: Schematic of the proposed pseudo-differential bulk-driven OTA
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4.2 Pseudo-Differential Bulk-Driven OTA with Enhanced DC-gain
In addition, a CMFB circuit is employed for the output stage. It will help in keeping the output common-mode node voltage to a known reference voltage (VREF). The details of the different stages are discussed in the sub-sequence subsections.
4.2.1 Input stage
A bulk-driven pseudo-differential pair comprises ofM1A,B−M3A,B used as the input stage of the proposed OTA. Differential inputsViN andViP are applied across the bulk terminal ofM1AandM1B. The input stage is loaded with diode connected pMOS transistorsM2A−M2B. Another pair of pMOS transistorsM3A−M3B, were configured in a cross-coupled mode to cancel gate transconductance and to enhance the gain of the input stage. The bulk terminals of M3A−M3B are also connected in a cross-coupled manner, which helps in further improvement of gain. For differential input signal, the cross-coupled pair acts as partial positive feedback and produces a negative transconductance which reduces the overall load conductance. This sets the differential-mode gain of the first stage to a high value. For common-mode input signal, the first stage gain is a low value, because the cross-coupled pair acts as negative feedback hence increases the overall load conductance.
4.2.2 Cross-forward stage
The CF stage formed with transistorsM4A,B−M6A,B, is a part of the output stage. The differential output of the first stage is attached to common source transistors M6A and M6B which are loaded with cross-coupled transistors M4A and M5B. This arrangement offers finite DC-gain for differential- mode signals, and enhances transconductance of output stage and overall DC-gain of OTA. It also helps to improve the stability of OTA for large capacitive loads. Moreover, the CF stage subtracts common-mode signals and offers a smaller common-mode gain, resulting in the improvement of CMRR of OTA.
4.2.3 Output stage
The output stage consists of two identical common-source transistor pairsM7A−M8Aand M7B− M8B. In order to obtain Class-AB operation at the output nodes, the differential output of CF stage is connected to M7A and M7B, transforming it into an active amplifying device. Here, CF stage acts as a current replication branch and also offers finite voltage gain. The load driving capability of OTA depends upon the output stage transconductance. For large capacitive loads, the Miller compensated OTAs require large transconductance at output stage [10]. For this, a high current is required at the
output stage to maintain the desired stability. Instead, the use of CF stage in the proposed design enhances the output stage transconductance with only a small current in the output stage.
4.2.4 CMFB stage
When the input common-mode voltage changes in fully-differential OTA architectures, the output node voltage will saturate to one of the supply rails due to the mismatch between transistors. Hence, we employed CMFB circuit for the proposed pseudo-differential OTA, to maintain the output common- mode voltage at reference voltage (VREF). The CMFB circuit in Fig. 4.1 is based on one discussed in [31]. The CMFB circuit, constituting transistors MC1 to MC4, performs the tasks of the common- mode detection and reference comparison. If there is any mismatch between output common-mode voltages of OTA, the feedback mechanism adjusts both the output node voltages to the desired value (i.e., VREF). The CMFB circuit offers finite gain and improves CMRR with common mode input.
The bandwidth of CMFB circuit should be more than that of OTA in order to avoid compensation for CMFB circuit.
4.2.5 Bias stage
In Fig. 4.1, the bias voltages VBP and VBN are generated using bias generator circuit [128]. The transistorsMT1−MT5with bias current sourceIBare arranged in a feedback configuration to generate bias voltages VBP and VBN. With this arrangement, the bias voltages will change according to the PVT variations.