Performance Enhancement Techniques for Low-Voltage Bulk-Driven Circuits

The gain of the bulk-driven input stage is improved with cross-coupling of active load transistor bulk terminals. 127 6.17 The DC gain, UGF and phase margin of the proposed OTA with and without SE, due.

Introduction

Motivation

Of these, the bulk-driven MOSFET is one of the most promising techniques for designing analog circuits in a low-voltage environment. The low-voltage circuits must provide rail-to-rail output swing to maximize SNR.

Problem formulation

The aim of this thesis is to develop energy-efficient crowd-controlled OTAs for low-voltage applications. Overall, this thesis aims to improve the performance of crowd-controlled OTAs in a low-voltage environment.

Contributions of the Thesis

Design of analog circuits with STI effect
A low-voltage PVT-insensitive bulk-driven OTA with enhanced DC-gain
An ultra-low-voltage bulk-driven OTA for low-frequency applications
Low-voltage Class-AB bulk-driven OTAs with improved slew rate

A PVT-insensitive bulk-driven OTA with enhanced DC gain for low-voltage applications is described. An ultra-low voltage pseudo-differential bulk driven OTA with enhanced transconductance for low frequency applications is presented.

Organization of the Thesis

In the first model, a low-voltage, high-conductivity Class-AB OTA with minimal current consumption is considered. In the second model, bulk-driven OTA with motion speed enhancer (SE) is considered which further improves the driving ability.

CMOS Technology Scaling Trade-offs

The fundamental limits limiting the design of low-power circuits are reviewed first with an emphasis on the implications of reducing the supply voltage. New design techniques suitable for low power and/or low voltage circuits are presented.

Scaling Trends in Analog CMOS Technologies

For each generation, a 30% reduction in gate length yields approximately a 50% reduction in gate area or a doubling of packing density. To ensure reliability with the reduction of device dimensions, a low voltage should be used.

Comparison of Low-Voltage Analog Circuit Design Techniques

Bulk Driven MOSFET: In this technique, the input signal is applied to the main part (backgate or body) of an input device while the gate is biased to create a conducting channel between source and drain [22]. The output resistance of a bulk-driven transistor is similar to that of a gate-driven counterpart.

State-of-art Bulk-driven OTAs

Enhancement of small-signal performance

In [30], bulk-driven OTA is implemented using flipped voltage follower to improve linearity and dynamic performance. The techniques presented so far are used to improve the transconductance and gain of bulk-driven OTAs.

Enhancement of large-signal performance

In these designs, the comparator detects the rising and/or falling edges of the input waveform to turn on a push/pull transistor to charge/discharge the output load [68]. In summary, the existing bulk powered topologies are not suitable for powering the large CL under low voltage environment.

Summary

Introduction

In [103], the effect of IST stress on the performance of real circuits is studied and the corresponding optimization strategies are established. In the proposed design procedure, initially, the design parameters are calculated using the gm/ID methodology for the desired circuit specifications.

Characteristics of Multifinger MOSFET

Drain current characteristics of multifinger MOSFET

Therefore, to achieve uniform circuit performance with multifinger devices, the design parameters are changed by using ID/W characteristics of the obtained NF. 3.1(b) that the change in ID could be as high as 60% in the sub-threshold region of the MOSFET, although it reduces to less than 10% as the device operating regime changes from weak inversion to strong inversion.

Figure 3.1: Characteristics of nMOS for V DS = 0.5-V, W = 20 µm, and L = 0.2 µm (a) I − V characteristics for different N F , (b) Relative error of I D with respect to N F = 1

Miller-Compensated Two-Stage OTA

The schematic of two-stage OTA and its small-signal equivalent model is shown in Fig. Here, CC is the compensation capacitance, C1 and Cout are the parasitic capacitances, and CL is the load capacitance. The voltage transfer function resulting from the addition of CC is given in (3.7), where gm1 (gm6) is the transconductance of the differential pair M1−M2 (output stage M6), and R1 (R2) is the output resistance of the first (second) stage.

Design Procedure for Two-Stage OTA

The phase margin (φM) of a two-stage Miller-compensated OTA is given by ThePN and ZN are determined from the φM of the amplifier. For each transistor, the gm/ID factor is first determined from the OTA design specifications. The normalized ID/W current for each transistor is then determined from the gm/ID and ID/W vs. VGS curves.

Fig. 3.5 shows the g m /I D , I D /W versus V GS characteristics for both nMOS and pMOS, obtained through simulations using a UMC 65-nm CMOS technology

Bulk-driven Current Mirror OTA

To achieve the desired GBW for a given load CL, from (3.31), either B and/or IB should be large. Furthermore, an increase in B leads to larger parasitic capacitances at nodes N1 and N2, which in turn reduces the phase margin.

Design Procedure for Bulk-driven Current Mirror OTA

Therefore, the gmb/ID properties can be used to find the geometry of bulk-driven MOS devices from the given specifications. These characteristics are used to size the bulk powered devices for different common mode input voltages. Step :2 The bias current of bulk driven differential stage bias depends on the GBW of OTA.

Figure 3.8: Characteristics of bulk-driven pMOS for V DS = 0.5-V, V BS = 0.25-V and W = 20 µm, and L = 0.5 µm (a)Transconductance-to-drain current ratio (g mb /I D ) characteristics of pMOS for different N F , (b) Relative error of g m /I D with respect to

Extraction of Design Parameters with STI Effect

Example: From Table 3.2, the transistorM5 should be represented as multiple fingers, since W5 = 16.5 µm, which is greater than 10 µm and NF of M5 is 2. From Table 3.3 it is clear that, compared to the direct scaling, the device finger width for the proposed method is smaller under the same bias condition. The design parameters for different test cases using direct scaling and the proposed method are shown in Table 3.6.

Table 3.1: Design specifications of two-stage OTA

Simulation Results

The performance parameters of bulk powered OTA obtained using the proposed and direct scaling methods are tabulated. Also, the bulk-powered OTA with direct scaling consumes more power due to STI effect. The layout of the bulk-driven TOA based on multifinger devices with direct scaling and proposed scaling is shown in Fig.

Figure 3.13: Simulated large-signal response (a) and its zoomed portion (b) of the multifinger OTA with STI effect (blue) and without STI effect (red).

Summary

This chapter discusses a PVT-intensive pseudo-differential bulk-driven OTA operating in a weak inversion region suitable for low-voltage applications. The amplifier uses a bulk controlled input for rail-to-rail input operation and a differential class AB output stage for rail-to-rail output swing. The proposed design uses a partial positive feedback technique to increase the low-frequency gain of the bulk-driven OTA.

Pseudo-Differential Bulk-Driven OTA with Enhanced DC-gain

Input stage
Cross-forward stage
Output stage
CMFB stage
Bias stage

A bulk-driven pseudo-differential pair consists of M1A,B−M3A,B which is used as the input stage of the proposed OTA. Instead, the use of CF stage in the proposed design increases the output stage transconductance with only a small current in the output stage. Therefore, we used CMFB circuit for the proposed pseudo-differential OTA, to maintain the output common-mode voltage at reference voltage (VREF).

Figure 4.1: Schematic of the proposed pseudo-differential bulk-driven OTA

Analysis of the Proposed High Gain OTA

Differential-mode analysis
Common-mode analysis
Noise analysis
Frequency compensation

This analysis is performed to understand the effect of the common mode signal on the output nodes (VOP and VON) by calculating the common mode gain (ACM). The CF stage reduces the transconductance of the output stage and thus lowers the common mode gain. The CMFB circuit acts as an amplifier for the common mode input and reduces the overall common mode gain of the OTA.

Figure 4.2: Small-signal circuit model of the proposed OTA for frequency analysis

Simulation Studies

The open loop magnitude and phase characteristics of the proposed amplifier at different loading conditions are shown in Fig. To verify the robustness of the proposed amplifier, simulations were performed for different PVT conditions. The parameters of the proposed OTA for different PVT cases are summarized in Tables 4.2, 4.3 and 4.4.

Figure 4.3: Simulated open-loop frequency response of the proposed OTA for different C L .

Performance Summary and Comparison

In addition to these, another FOM is required to reflect the efficiency of DC gain and low voltage operation. Since, the OTA proposed in this chapter is mainly designed to achieve high gain in low voltage operation. Another FOM is also calculated to reflect low voltage operation and is given by [26].

Figure 4.11: Layout of the proposed bulk-driven OTA.

Summary

At much lower supply voltages, the tail current source can be removed without much degradation in circuit performance, so an amplifier normally referred to as pseudo-differential amplifier is considered in this work. A new ultra-low-voltage, ultra-low-power pseudo-differential bulk-actuated OTA is presented in this chapter. The proposed design uses an auxiliary circuit at input stage to improve the effective transconductance of bulk-driven OTA.

Pseudo-Differential Bulk-Driven OTA Circuit Design

Bulk-driven pseudo-differential input stage

The modified bulk-driven pseudo-differential input stage with auxiliary stage is shown in Fig. The proposed input stage design provides higher DC gain and transconductance compared to the conventional design. 5.3) where, gmbI is the effective transconductance of the bulk-driven input stage with auxiliary amplifier from (5.2).

Differential output stage

The Class-AB structure of output stage reduces the common-mode gain because common signal in one path cancels the signal in another path due to 180◦ phase difference. The transconductance of output stage depends on the gain of intermediate stage (i.e. cross-forward stage) and current in output stage. The proposed OTA achieves a large transconductance at output stage with a small amount of additional current through cross forward stage.

CMFB stage

To increase the transconductance of the output stage, the output of the first stage is connected to M9A,B and M7A,B. The output of the first stage and the forward crossover stage are connected to the gates of M7A, B and M6A, B, respectively. The difference between these two currents changes the common-mode feedback voltage (VCM F B) and is fed back to the larger terminal of the output stage transistors (ie, M7AandM7B).

Analysis of the Conventional and Proposed Bulk-driven OTAs

Analysis of Differential-Mode Configuration

Analysis of Common-Mode Configuration

Noise analysis

PSRR analysis

Frequency Compensation

Simulation Results of Pseudo-Differential Conventional and Proposed OTA

The effective transconductance of the proposed OTA is higher than that of the conventional OTA model. It sets the desired output node voltage by adjusting the larger voltage of M7A and M7B. The DC gain of the CMFB circuit with common mode input signal is given by. The CF stage increases the overall DC gain of the proposed OTA and the auxiliary circuit in the input stage improves the effective transconductance.

In order to examine the robustness of the proposed OTA against process variations and misalignment, Monte Carlo simulations were performed and the results are summarized in Table 5.5. Table 5.5 shows that the proposed OTA is robust against process variations as the parameters are less than 10% sensitive. The magnitude and phase response obtained by Monte Carlo simulation for 1000 runs are shown in Figure 1.

Figure 5.15: Magnitude and phase response of Monte Carlo simulation for 1000 samples (I B =10 nA).

To observe the filter response due to process variations, the Monte-Carlo analysis of biquad filter is performed for 1000 samples at different bias current IB = 10 nA. 5.21(b) that the deviation in the cutoff frequency of the filter due to process variation is within the acceptable limit with a relative error of 3.3%.

Figure 5.19: Simulated frequency response of the G m − C biquad filter.

Comparative Studies

Summary

Another way to achieve a high OTA slew rate is to increase the current in the active load of the differential input stage. The existing topologies discussed so far either require a large bias current to improve the slew rate or require a high supply voltage, which in turn consumes more power. Therefore, in this chapter, we proposed low-voltage class AB crowd-driven OTAs with improved slew rate.

Proposed Circuit Implementation

Adaptive biasing

The UGF and output current of Class-A OTA in weak inversion region is given by. This is due to the fact that for large Vid the output current of Class-AB OTA is not limited by input stage bias current IB. On the other hand, the Class-AB OTA output current is much larger than bias current 2IB.

Figure 6.1: Schematic of current mirror OTA (Class-A) [2].

Adaptive loads

Low-Voltage Super Class-AB Bulk-Driven OTA with Adaptive Biasing and Adaptive

It can be seen from (6.4) that for largeVid, the maximum output current of the Class A OTA is limited to 2BIB, which causes a reversal at the output node. In a Class AB OTA, the dynamic current increases by a large Vid and is greater than the level of the input quiescent current. the output current expression of a class AB OTA is given by. The CBF mainly depends on the output current of the OTA and the bias current of the input stage in the quiescent state.

Low-Voltage Class-AB Bulk-Driven OTA with Slew rate Enhancer

The current feedback loop in the slew rate amplifier creates a partial positive feedback that improves the DC gain of the OTA. An approximate analytical expression for the DC gain of the speed-of-turn acceleration circuit (ADC,SE) can be written as It can be seen from (6.16) that the combination of adaptive preload and adaptive load with a turning speed amplifier increases driving performance and significantly improves turning speed.

Figure 6.7: Schematic of Class-AB bulk-driven OTA with slew rate enhancer.

Simulation Results

The open-loop frequency response of the proposed OTA with and without SE is shown in Fig. illustrated. The average rotation rate of the OTA with SE is 0.93 V/µs which is 10 times that of the rotation rate of the OTA without SE. The transient responses of the proposed OTA with and without SE for different load capacitors are shown in Fig.

Figure 6.9: Open-loop frequency response of the proposed bulk-driven OTAs.

Performance Comparison

Summary

The Miller-compensated two-stage OTA and bulk-driven current mirror are selected as example circuits for validation of the proposed methodology. The gain of the bulk-driven input stage is improved by the use of cross-coupling of bulk-terminal of active load transistors. An ultra-low-voltage pseudo-differential bulk-driven OTA with rail-to-rail input/output swing is designed for low-frequency applications.

Future Work

Shih, “An ultra-low-voltage cmos process-insensitive self-biased ota with rail-to-rail input range,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. Islam, “Low-voltage bulk-driven operational amplifier with enhanced transconductance,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. Chavero, "The Flipped Voltage Follower: A Useful Cell for Low-Voltage Low-Power Circuit Design," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.