Hardware Architecture of Low-Power ALU using Clock Gating

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International Journal of Recent Advances in Engineering & Technology (IJRAET)

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ISSN (Online): 2347 - 2812, Volume-3, Issue -12, 2015 32

Hardware Architecture of Low-Power ALU using Clock Gating

1M V Ganeswara Rao, ²P Ravi Kumar, ³GRLVN Srinivasa Raju

1,2,3 Shri Vishnu Engineering College for women, India

Abstract: With the scaling of technology, need for high performance and more functionality, power dissipation becomes a major bottle neck for microprocessor systems design, because clock power can be significant in high performance systems. We propose a low power ALU for high performance systems, which make use of clock gating to reduce clock power. This low-power ALU based on the observation that while one functional unit is working other functional units remain ideal, but they are connected to clock and dissipating significant amount of power. By using clock gating technique we achieved significant amount of power saving at high frequency operations. Functionality of proposed ALU is tested using Xilinx 12.1i software tool.

Power analysis of ALU done by using Xilinx’s xpower power analysis tool. It is observed that designed ALU dissipating power of 24 mw when it is operated at the clock frequency of 15 MHz and supply voltage of 2.4V under load current of 16 mA. ALU is successfully implemented on Xilinx Spatran 3E FPGA.

Keywords: Clock gating, Xilnix, Xpower

I. INTRODUCTION

Present day General purpose microprocessor designs are faced with the daunting task reducing power dissipation.

Since power dissipation is quickly becoming bottle neck for future technologies [1][2]. Lowering power consumption is important for not only lengthening battery life in portable systems. But also improving reliability and reducing heat removal cost in high performance systems [3][4].

Clock power is major component of microprocessor power, because the clock is fed to most of circuit blocks, including ALU. Total power dissipation of chip consists of two components. 1. Static power dissipation which is due to leakage current of transistor during stead state and it is very small so, it is neglected 2. Dynamic power dissipation which has two components (a) Short circuit power dissipation which is a function of slew rate and by applying sharp clock edges, this power dissipation is very small and is neglected. (b) Charge/ discharge power dissipation which is given by

P = f.C_L V_dd Vs (1)

Where f is the frequency of the clock, C_L is the load capacitance, V_ddis the supply voltage and V_s is output swing. When output swing from 0 to V_dd then

P = f.C_L V_dd2

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We should not reduce power supply voltage very low value since there are various problems associated with lowering the voltage, in CMOS circuitry the drivability of MOSFET will decreases, signal become smaller moreover increase in gate delay time when operating voltage reduced to 2V or less. Reducing clock frequency affects the performance of the system. To reduce the power consumption without scarifying the performance of the system, we adopted clock gating technique in our proposed ALU architecture [5][6]. The functionality of proposed architecture verified using Xilinx 12.1i and power is analyzed using Xilinx’s xpower power analysis tool.

II. PRINCIPLE OF CLOCK GATING

The schematic of latch element shown in Fig. 1(a), Cg is the latch’s cumulative gate capacitance connected to the clock because clock switches every cycle. The Cg charges and discharges every cycle consumes significant amount of power even if the input do not change from one cycle to the next, latch still consumes clock power [7][8][9]. In fig. 1(b) the clock is gated by AND gate with control signal referred as Clk- gate signal. The latch input which is not required to change one clock cycle to another for that Latch Clk-gate signal is turned off and clock is not allow to charge/discharge the Cg, hence this saves clock power.

Since a single AND gate used to drive Latches of size 32 bit or 64 bit, the capacitance introduced by this AND gate is much smaller than sum of multiple Cg of these latches. hence we can achieve net power saving.

Figure 1 : Clock Gating a Latch PROPOSED ARCHITECTURE

Proposed 16 bit ALU performs 16 bit Arithmetic and logical operations selected by 4 operation select lines (opcode). Fig. 2 shows inputs and outputs of proposed

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ALU. Instead of designing ALU as single module, divide ALU into four functional blocks namely Arithmetic1, Arithmetic2, Logical1 and Logical2

Figure 2 : Back box view of proposed ALU Fig. 3 shows the proposed ALU Architecture. Each block perform four different operations as shown in the functional Table .1.

While arithmetic1 is performing operations remaining functional blocks Arithmetic2, Logical1 and Logical 2 are not performing any operations. In order to reduce power consumption by at these nonfunctional blocks, apply the clock to these blocks through two AND gate with Clk-gating signal as other input. This clock gating signal is generated by decoder and controls the charge/discharge power dissipation at the input of unused functional blocks. Similarly when one functional block is performing operations the charge/discharge capacitance at the clock input of remaining blocks are controlled and clock power is saved. Two out of four select lines are used to select required operation in functional and also used to generate clk-gating signal, remaining two lines used to select appropriate output

from four outputs of four functional blocks with the help of MUX.

Table-1 : Functional Block Status For Each Input Opcode Operation Active

functional block 0000 Addition

Arithmetic1 0001 Subtraction

0010 Increment 0011 Decrement 0100 Multiplication

Arithmetic2 0101 Add with carry

0110 Clear Reg 0111 Set Reg

1000 NOT

Logical1

1001 AND

1010 OR

1011 EXOR

1100 Shift left

Logical2 1101 Shift Right

1110 Rotate left 1111 Rotate right

IV. IMPLEMENTATION OF LOW-POWER ALU

whole design is captured using VHDL language.

Different blocks in architecture are implemented as different modules and finally they are connected to get the final result. The following steps are followed during implementation of this design i)Code generation ii) Simulation iii) place & root iv) Floor planning v) Synthesis vi) Power analysis (using Xilinx’s Xpower)

Figure 3 : Proposed ALU Architecture

V. RESULT

The designed Low power ALU is successfully implemented on Xilinx Spartan 3E FPGA and design simulated using ISE simulator. The simulations for

various test vectors are shown in Fig. 4. Xilinx’s Xpower analysis tool is used to estimate the power dissipation of

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Low-power ALU and the power dissipation of designed ALU operating at various clock frequencies from 0- 15 MHz is shown Fig. 5 Similarly power dissipation of ALU for the various load currents are shown in Fig. 6.

By analyzing above result, it is observed that power consumption increases as frequency of the clock and load current increases.

A conventional ALU also implemented without using Clock Gating and power estimations are generated.

It also observed that Proposed ALU consumes less power compared to conventional ALU at particular frequency, supply voltage and load current.

Figure 4 : Simulation Results

Figure 5 : Power Dissipation Vs Load current

Figure 6 : Power Dissipation Vs Frequency

VI. CONCLUSIONS

A Low Power ALU successfully captured using VHDL and implemented on Xilix Sptran 3E FPGA. The

proposed ALU can perform 16 functions, Which include arithmetic, Logical and shift operations. The proposed ALU will dissipate 24mW of power at 15Mz of clock,

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the characteristics of ALU is summarized in Table II.

The designed ALU core can be used in any high performance systems such as high speed processors. By employing Clock gating, we can design f low power RISC processor which consumes less power at high execution speed.

Table :2 Characteristics of ALU Chip Power Dissipation 24mW @15MHz Supply Voltage 2.4V

No. of functions 16

ACKNOWLEDGMENT

This paper is supported by Dept. of Electronics and communications and TI DSP laboratory of Shri Vishnu Engineering College for Women.

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