SUBMISSION OF FINAL YEAR PROJECT

The development of this project will begin with the design of the ADC controller unit. The ADC controller unit and internal block will be modeled using Verilog HDL. The specifications of the ADC controller unit and the instantiation of the ug480 will be functionally verified by writing testbenches in Verilog HDL.

It involves the interface between the ADC controller and the RISC32 based on the I/O memory mapping technique.

INTRODUCTION

Background Information

MIPS
ADC

Motivation
Problem Statement
Project Scope
Project Objectives
Impact, Significance, and Contribution

Furthermore, an Interrupt Service Routine (ISR) will be developed specifically to handle the interrupt request generated by the ADC controller unit. In addition, a complete documentation of the ADC controller unit will be produced at the end of the project. It is important to ensure that the verification specifications for the ADC controller unit are well developed before proceeding to the physical design phase.

A well-developed fully functional interfacing system between the CPU and the ADC controller unit in the form of synthesis-ready RTL that is written in Verilog HDL.

LITERATURE REVIEW

Overview of Xilinx XADC

Each status register has a special name and function to store the converted value from different channels. The XADC has two modes of operation, namely single channel mode and continuous sequence mode. In continuous sequential mode, the user can choose to monitor multiple analog input values, and there are some additional configurations that can be made for sequential mode itself.

For example, if 16 average samples is selected, the XADC will capture the analog input 16 times and average it before storing it in the respective status register as in [15].

Figure 2-2: XADC Register Interface extracted from [15].

Memory-mapped I/O

When the analog input value does not fall within the threshold, it will trigger the alarm as shown in [15]. In order to have full control over XADC, the role of each registers must be understood and all the detailed information about the registers can be reviewed in attachment. No new dedicated instructions are required in MMIO to simply read or write those special addresses because it allows the normal load and store instructions to be used for referencing, manipulating, and controlling both memory and I/O devices.

The memory address being used will determine what type of device (memory or I/O device) it will be accessing.

ADC controller designed in [2]

Documentation should be done carefully to help clarify the address space allocated for each I/O device register. The benefits of using MMIO is that it keeps the instruction set small while respecting the design principles of MIPS, which is to keep the hardware simple through regularity as shown in [8].

PROPOSED METHOD/APPROACH

Methodologies and General Work Procedures

RTL Design Flow
Micro-architecture Specification
RTL Modelling and Verification
Logic Synthesis for FPGA

Design Tools

ModelSim SE-64 10.5
Xilinx Vivado Design Suite
PCSpim/QtSpim

Technologies Involved

Field Programmable Gate Array (FPGA)

Implementation Issues and Challenges
Timeline …

Gantt Chart for Project I
Gantt Chart for Project II

The internal design of the ADC controller will be described with detailed design-specific technical information so that the RTL coding can begin. With the development of the microarchitecture specification, RTL coding on the ADC controller can begin. As previously mentioned, the logic synthesis of the ADC control unit will ultimately be performed on FPGA technology.

The ADC controller in this project will interface with the XADC from Xilinx, which will also be instantiated in RISC 32.

SYSTEM SPECIFICATION

System Overview of the RISC32 Pipeline Processor

RISC32 Pipeline Processor Architecture
Functional View of the RISC32 Pipeline Processor
Memory Map of the RISC32 Pipeline Processor

Chip Interface of the RISC32 Pipeline Processor
Input Pin Description of the RISC32 Pipeline Processor
Output Pin Description of the RISC32 Pipeline Processor
Input Output Pin Description of the RISC32 Pipeline Processor

Pin name: uorisc_ua_tx_data Pin class: data source → Destination: crisc → UART unit of external device. Pin name: uiorisc_spi_mosi Pin class: data source → Destination: crisc ↔ SPI unit of external device Pin function: SPI standard pin – Master out Serial In (MOSI). Pin Name: uiorisc_spi_sclk Pin Class: Control Source → Destination: crisc ↔ SPI unit of external device.

Pin Name: uiorisc_spi_ss_n Pin Class: Control Source → Destination: crisc ↔ External device SPI device.

Figure 4-1: An overview on the architecture of the RISC32 pipeline processor as shown in [9] with UADC added

MICRO-ARCHITECTURE SPECIFICATION

Functionality/Feature of the ADC Controller Unit

Unit Interface of the ADC Controller Unit

Input Pin Description of the ADC Controller unit

Pin Name: uiadc_wb_r_addr[5:0] Pin Class: Control Source → Destination: Data Path Device→ ADC Controller Device Pin Function: Used to select which register to read. Pin Name: uiadc_wb_r_we Pin Class: Control Source → Destination: Address Decoder Block → ADC Controller Unit. Pin Name: uiadc_wb_r_stb Pin Class: Control Source → Destination: Address Decoder Block → ADC Controller Unit.

Pin Name: uiadc_wb_clk Pin Class: Global Source → Destination: Global Clock → ADC Controller Unit Pin Function: Global Clock. Pin Name: uiadc_wb_rst Pin Class: Global Source → Destination: Global Reset → ADC Controller Unit Pin Function: Global Reset. Source → Destination: Priority Interrupt Control Unit → ADC Controller Unit Pin Function: To allow the ADC to interrupt.

Pin Function: Receive the data ready signal, indicating that new data is ready to be read from the XADC. Pin function: receiving the end-of-conversion signal to indicate that the new data has finished being converted and a read operation can begin. Pin Function: Receive address to store new converted data into status register Pin Name: uiadc_ALM[7:0] Pin Class: Control.

Output Pin Description of the ADC Controller Unit

Internal Operation of the ADC Controller Unit

Example application of XADC with ADC Controller Unit in RISC32

Design Partitioning of the ADC Controller Unit

Micro-Architecture of the ADC Controller Unit

ADC Clock Control block

Functionality/Feature of ADC Clock Control block
Block interface of ADC Clock Control block
Input Pin Description of the ADC Clock Control block
Output Pin Description of the ADC Clock Control block

Pin Function: Address to store 16-bit data in SREG Pin Name: boadcclk_ctr_clk Pin Class: Control Source → Destination: ADC Clock Control → uadc Pin Function: Generate clock for data storage in SREG.

Table 5-6: Output Pin description of the ADC Clock Control block.

Finite State Machine of the ADC Controller Unit

Flags in FSM
Internal Operation: UADC to XADC
Internal Operation: XADC to UADC

While flag_UADC_READ depends on the End of Conversion (EOC) signal output from XADC when there is a new analog signal converted. When the flag is raised due to the wishbone write input, the next clock cycle will send enable(uoadc_DEN) and write enable (uoadc_DWE) signal to the XADC, to write the data in UADC_CREG to the configuration register at address 40h. The SET_WAIT state is required to wait for the uiadc_DRDY signal, which indicates that data has been successfully written into XADC.

After that, FSM returns to the SET_IDLE state and jumps to the next state according to the flag register. While the use of the previous state is to determine which flag to lower after the uiadc_DRDY signal. In fact, it is the Dynamic Reconfiguration Port (DRP) in XADC that receives the uoadc_DEN, uoadc_DWE, uoadc_DADDR, uoadc_DI and also sends the uiadc_DRDY signal.

The READ_ADC state is to continuously update the UADC_SREG in the ADC controller unit whenever a new analog value is converted. Therefore, flag_UADC_READ will be raised one clock cycle after the End of Conversion signal (uiadc_EOC) has been asserted, indicating that the next state will be READ_ADC. During the READ_ADC state, uoadc_DEN must be '1' and uoadc_DWE must be '0' in order for the XADC to perform the read function.

The register address (uoadc_DADDR) to read is the same as the CHANNEL output signal of XADC indicating the address of status register. While the uiadc_DRDY in this case will indicate that the data has been successfully read out from the XADC status register and temporarily stored in ADC clock control block.

Figure 5-6 Schematic diagram for the flag registers

Register Set

Normally, MSB is used to detect the occurrence of an alarm because it is the OR logic for the remaining 7 bits.

FIRMWARE DEVELOPMENT

Exception Handler of the RISC32 Pipeline Processor

Interrupt Service Routine (ISR) of the ADC Controller Unit

6:0], and is used in the ADC controller unit with the uiadc_ADCIE (ADC interrupt enable) to generate the Interrupt Request Signal (uoadc_IRQ). As mentioned in the previous section, only the temperature and VCCINT alarm threshold register are implemented. Therefore, in this project, only the threshold of the temperature and VCCINT sensors can be configured in XADC, which is enough to observe the simulation result and verify the functionality.

Additionally, a simple interrupt service routine is designed for the ADC controller unit to perform certain actions. For example, if it is temperature sensor (ALM [0]) that activates the interrupt request signal, GPIOEN [0] will be set to '1'. Consequently, the user can apply this function in some home automation project, such as activating the cooling system when the temperature is too high or activating the siren when the sensor's value falls into unwanted range.

In this example, each GPIO is assigned six internal sensor measurements (temperature, VCCINT, VCCAUX, VCCBRAM, VCCPINT, . VCCPAUX, VCCO_DDR).

Figure 6-2 below shows the pseudocode of the developed ISR for handling interrupt request from the ADC controller unit

VERIFICATION SPECIFICATION AND SIMULATION

Unit Level Functional Test Plan
Simulation Result for Unit Level Functional Test

Test case 1: System Reset
Test case 2: Read Operation
Test case 3: Write Operation
Test case 4: Interrupt Operation

Testbench for Integration Level Functional Test
Simulation Result for Integration Level Functional Test

Around hour 140, the Vccint alarm will be lower, but the temperature alarm will remain high at 70oC. To verify that the simulation result shown in the waveform is correct, the analog value in the stimulus file is converted using the formulas attached in the Appendix. During 140us, the alarm signal for Vccint(ALM[1]) will be removed as it is 1.0V, while the alarm signal for temperature (ALM[0]) will stay high to have 70oC. ii) Type TEMP_MIN_THRESHOLD to change the low threshold value to 70 oC.

Changing the threshold to 70oC ≤temp≤85oC will now reset alarm signal (ALM[0]) for temperature. iii). Interrupt request signal (tb_op_IRQ) will be '0' even there is presence of alarm signal due to the interrupt enable signal (uiadc_ADCIE) has been reset.

Table 7-1: digital value of stimulus file.

MULTIPLE IO SYSTEM FUNCTIONAL TEST

Test Case: Multiple interrupt and Multiple Trap

While for ADC interrupt, it is enabled by the power supply VCCINT when the value exceeds 1.05V. At the same time, multiple traps were deliberately programmed on the server side (DUT) to see if any exception events would collide with each other. Again, all exception events are expected to be properly serviced with their respective ISR executing, which means that if there is IRQ, we should see the initial program counter be stopped and stored in a register $epc before the program counter goes to the respective ISR jump.

When the ISR is done, the program counter returns to the previous program by reading the value in $epc. When multiple interrupts occur, all exception events must be handled according to the priority level without any conflict. External exceptions originating from all IO devices have the highest priority over internal exceptions such as Syscall, Undefined Instruction, and Sign-overflow.

While the priority level between the external exception is defined by the user by setting the register in the Priority Interrupt Controller as mentioned in [14]. However, in this test case, the values are all defaults and the priority will depend on the vector number of the IO device.

Figure 8-2: The time when the interrupt happens for ADC.

Testbench for Multiple Exception Test

Simulation result

Unlike the UART interrupt as shown in [5], there is no conflicting exception between Trap and Interrupt where the two or more IRQ occur in the same clock cycle. The best sequence we can get is ADC interrupt triggered one clock cycle earlier than Trap.

CONCLUSION AND FUTURE WORK

Conclusion

Future Work

Lecture notes distributed at Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman. MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX (MEASURED_AUX0), .MEASURED_VCCAUX (MEASURED_VCCAUX). Faculty of Information and Communication Technology (Kampar campus), UTAR .uiadc_wb_r_we(tb_ip_wb_r_we), //WRITE ENABLE.