TEKNIK DIGITAL (A) (TI 2104)

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TEKNI K DI GI TAL (A)

(TI 2104)

Mat er i

Kuliah

ke

-

10

10 Count ers

Count ers

4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7) 2

Overview

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n Ripple Count erRipple Count er

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n Synchr onous Binar y Count er sSynchr onous Binar y Count er s

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n Design wit h D FlipDesign wit h D Flip--FlopsFlops n

n Design wit h JDesign wit h J--K FlipK Flip--FlopsFlops

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n Ser ial Vs. Par allel Count er sSer ial Vs. Par allel Count er s

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n UpUp--down Binar y Count erdown Binar y Count er

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n Binar y Count er wit h Par allel LoadBinar y Count er wit h Par allel Load

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n BCD Count er , Ar bit r ar y sequence Count er sBCD Count er , Ar bit r ar y sequence Count er s

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Count ers

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n A A count ercount er is a r egist er t hat goes t hr ough a is a r egist er t hat goes t hr ough a pr edet er mined sequence of st at es upon t he

pr edet er mined sequence of st at es upon t he

applicat ion of clock pulses.

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n Count er s ar e cat egor ized as: Count er s ar e cat egor ized as:

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n Ripple Count er s: Ripple Count er s:

The FF out put t r ansit ion ser ves as a sour ce f or

t r igger ing ot her FFs. No common clock.

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n Synchr onous Count er :Synchr onous Count er :

All FFs r eceive t he common clock pulse, and t he

change of st at e is det er mined f r om t he pr esent

st at e.

Example: A 4

-

bit Upward

Count ing Ripple Count er

Recall... Less Signif icant Bit out put is Clock

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4- Feb - 09 Chapt er 5 - ii: Regist er s (5.4- 5.7) 5 r eceives t he incoming clock pulses.

r eceives t he incoming clock pulses.

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complement ed wit h each

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Use dir ect Set (S) signals inst ead of

dir ect Reset (R), in or der t o st ar t at 1111.

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Alt er nat ive designs:

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n Change edgeChange edge--t r igger ing t o posit ive (det ails in t r igger ing t o posit ive (det ails in class)

class)

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n Connect t he complement out put of each FF Connect t he complement out put of each FF t o t he C out put of t he next FF in t he

t o t he C out put of t he next FF in t he

sequence… (homewor k!)

A 4

-

bit Downward

Count ing Ripple Count er

Using D Flip-Flops

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Synchr onous Binar y Count er s

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n The design pr ocedur e f or a binar y count er is The design pr ocedur e f or a binar y count er is t he same as any ot her synchr onous sequent ial

t he same as any ot her synchr onous sequent ial

cir cuit .

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n The pr imar y input s of t he cir cuit ar e t he CLK The pr imar y input s of t he cir cuit ar e t he CLK and any cont r ol signals (EN, Load, et c).

and any cont r ol signals (EN, Load, et c).

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n The pr imar y out put s ar e t he FF out put s The pr imar y out put s ar e t he FF out put s (pr esent st at e).

(pr esent st at e).

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n Most ef f icient implement at ions usually use TMost ef f icient implement at ions usually use T- -FFs or J K

FFs or J K--FFs. We will examine J K and D f lipFFs. We will examine J K and D f lip-

-f lop designs.

f lop designs.

J -K Flip Flop Design of a 4-bit Binar y Up Count er

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J -K Flip Flop Design of a Binar y Up Count er (cont .)

Synchronous Binary Count ers:

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J_{Q 0}= 1 K_{Q 0}= 1

J_{Q 1}= Q₀ K_{Q 1}= Q₀

J_{Q 2}= Q₀Q₁ K_{Q 2}= Q₀Q₁

J_{Q 3}= Q₀Q₁Q₂ K_{Q 3}= Q₀Q₁Q₂ J

K C

J

K C

J

K C

J

K C

CLK

logic 1 _Q

0

Q₁

Q2

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J -K Flip Flop Design of a Binar y Up Count er wit h EN and CO

EN = enable cont r ol signal, when 0 count er r emains in t he same st at e, when 1 it count s

CO = car r y out put signal, used t o ext end t he count er t o mor e st ages

J_{Q 0}= 1 · EN K_{Q 0}= 1 · EN JQ 1 = Q0 · EN

K_{Q 1}= Q₀· EN J_{Q 2}= Q₀Q₁· EN K_{Q 2}= Q₀Q₁· EN J_{Q 3}= Q₀Q₁Q₂· EN KQ 3 = Q0 Q1 Q2 · EN

C0 = Q₀Q₁Q₂Q₃· EN

• D_Q0= Q₀⊗ EN

• D_{Q 1}= Q₁⊗ ( Q₀· EN) • D_Q2= Q₂⊗ ( Q₀Q₁· EN ) • D_Q3= Q₃⊗ ( Q₀Q₁Q₂· EN ) • C0 = Q₀Q₁Q₂Q₃· EN

See Figur e 5- 11… compar e wit h Figur e 5- 11: J K- based design calls f or 4 AND gat es

D- based design calls f or 4 AND and 4 XOR gat es

Synchr onous binar y count er s

using D f lip

-

f lops

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Serial Vs Parallel Count ers

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1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 0 1 1

1 1 0 1 1 0 0

1 1 1 0 1 0 1

1 1 1 1 1 1 0

UD Q2 Q1 Q0 Q2.D Q1.D Q0.D

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 0 1 1

0 0 1 1 1 0 0

0 1 0 0 1 0 1

0 1 0 1 1 1 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

UD Q2 Q1 Q0 Q2.D Q1.D Q0.D

Up-Counter Down-Counter Up-Down Binary Counter (cont.)

UD Q2 Q1 Q0

00 01 11 10

00

01

11

10

Fill- in t he Kar naugh maps f or Q2.D, Q1.D, and Q0.D, simplif y, and der ive t he logic diagr am using

(a) D-FFs and (b) T -FFs

Up

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Ar bit r ar y Sequence Count er

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n Given an ar bit r ar y sequence, design a count er Given an ar bit r ar y sequence, design a count er t hat will gener at e t his sequence.

t hat will gener at e t his sequence.

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n Pr ocedur e:Pr ocedur e:

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n Der ive st at e t able/ diagr am based on give sequenceDer ive st at e t able/ diagr am based on give sequence n

n Simplif y (using KSimplif y (using K--maps, et c)maps, et c) n

n Dr aw logic diagr amDr aw logic diagr am

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n Example: Use DExample: Use D--FFs t o dr aw t he logic FFs t o dr aw t he logic diagr am f or sequence gener at or (count er )

diagr am f or sequence gener at or (count er )

f or : 0

f or : 0 _à_à 7 7 _à_à 6 6 _à_à 1 1 _à_à 0 0 (000 (000 _à_à 111 111 _à_à 110 110 _à_à

001