5 . 8 DESIGN PROCEDUR E

Designprocedu resor methodologies specify hardwarethat will implementadesiredbehavior.

Thedesigneffort forsmallcircuits may bemanual.but industryrelies on automatedsynthesis

226 Chapter 5 SynchronousSequential Logic

tool s for design ing massive Integrated circuits.The building block used by!>ymhc!>i!>tool .. is theDflip-flop.Togetherwith additionallogic.itcantmple memthebehavior ofJKandTflip- flops.Infact.designersgenerallydonotconcern themselveswiththetypeof flip-flop: ramer.

the ir focus is oncorrectlydescribi ngthesequentialfunctionalityIhatistobeimplemented by thesyn thesis tool ,Here we will illustrat emanu al methodsusin gD.JK.andTflip-flops,

Thedesignofaclockedsequentialcircuitstartsfro m a setofspecificati ons and culminate..

in alogic diagramor alist of Booleanfunction s from which the logic diagramcanbeobtained.

Incontrastto a combinat ional circu it...hichis fully ..pecified b)'a truth table. a sequential cir- cuitrequiresastaretable forits specifica tio n.The firststep in the design of sequential circuits isto obtai nastate tableoranequivalentrepresent at ion. such as a Slate diagram.

Asynch rono us..equential circuitismade up offlip-flops and combination algate....The de- signof the circuitconsistsof choo singthe flip-flopsand thenfindinga combinationalgatestruc- ture mat. togetherwith theflip-flops.produce s a circuitwhich fulfillsthestaledspecification...

Thenumber ofFlip-flo psisdeterm inedfrom the numberofstates needed in the circuit.The combinationalcircuit is derived from thestate table byevaluating theflip-flop input equation s andoutputequations. Infact. oncethe type andnumberofflip-flops aredeterm ined.the design processinvol ves atransformationfromasequential circuit problem into a combinationalcircuit probl em.In this way.thetechniquesof combinational circuit design can be applied .

Theproced ure fordesigning sync hro nousseq ue ntialcircu its can besummariz ed by aIi..tof recom mended steps;

I. From the word description andspecific ationsof the desired operation .deri ve astale diagram for the circui t.

2. Reducethe number of states if necessary.

3. Assignbinaryvaluestothe states.

4. Obtai n the binary-codedSlatetable. S. Choosethe type offlip-flopstobeused.

6. Derivethe simpli fiedflip- flop input equationsand output equations.

7. Dra w the logicdiagra m.

The...ord spcctncn ionofthe circuitbehaviorusually assumesthat the readerisfamiliar ...ith digitallogicterminology.It isnecessarythatthe designeruse intuition and experience to ar- rive at the correct interp retation of the circuitspec ificat ion".because word descripti on s may beinco mpleteand inexact. Once suchaspeci fication hasbeen set down andthestatediagram obtuined. iti...j:>().s.sibJe /0useknownsynthesis proCt'(1ure.sro complelethedesign.Althoughthere areformal procedures forstate reductio nand assignment(steps2 andSj. tbeyare seldom used byexperienceddesign er s.Steps4 throug h7 in the designcanbeimp lementedbyexac talgo- rithmsand the reforecanbeautomated.The panof thedesignthatfollowsawell-defined pro- cedureis referred [0 assynthesis.Design ers usinglogicsynthes is tools (software)canfollo w a simplifiedprocessthatdevelops anHDLdescription directlyfrom astate diagram.Jett ing the synthesis1001 determinethe circuitelementsandstructure that implement thedescription.

11)e first step is a critical pan of theproc ess. because succeedingsteps depe nd on it.We ...iII giveone simple example to demonstrate how a stale diagr am is obtai ne d from a .... ord specification.

Sect ionS.8 Design Procedure 227

0

0

I

S ,,.,

0 0

•

SJi1 SliD

FIGURE5.27

State diagram for seque nce detector

Suppose we wishto designa circuitthatdetectsasequ ence ofthree or more consecut ive l's in astri ng of bitscoming throughan inputline (i.e..theinputisaseria l bit stream).The state diagramforthistypeof circuit is showninFig.05.27.It isderivedbystarting withstate So.the resetstate.If the input isO.thecircuitstays inSo.but ifthe inputis I.il goes10 state51toin- dicate thata Iwasdetected.Ifthenextinputis I,thechange is tostate S2to indicatethe ar- rivalof two consecuti ve t's,bUI ifthe input is0,the...talegoes backtoSo.Thethird consecutive I sendsthe circuit to stare 53'Ifmore I'saredetected,thecircuitstaysin5_{J •}Any0input sends the circuitback toSo-In thisway.the circuitstays in 53as longasthereare threeormorecon- securive 1'5received.This is aMoo remodel sequential circuit , since theoutputi... I when the circuit is instate53and is0otherwise.

Synth~sls

Using

0

F lip-F lops

Once thestare diagram basbeenderived,the rest of thedesignfollowsastraightforwa rd syn- thesi sprocedure.Infact,we can designthecircu itbyusingan HIJL descriplion ofthestate di- agramandthe proJX'r HOLsynthesis1001..10 obtaina synthe..izednetlist.(TheHp l. descnprion ofthestatediagram willbesimilartoHOLExamp le5.6 in Section5.6.)Todesignthecircuit by hand.we needto assignbinary codes 10 the slates andlistthestate table.Thisisdone in Table 05.1I.The table is derived from the Stalediagramof Fig.5.27witha sequentialbinaryas- signment. We choose twoDflip-flops 10 represent the fourstates, andwe labe ltheir outputs AandB.Thereisoneinput.r andoneoutputj-,The characteris ticequationof theDflip-flop isQ(t

+

I) = D_Q,whic hmeans that the next-state valuesinthe state table specifythelJinput conditionforthe flip-flop.The flip-flop input equat ionscan be obtaineddirectlyfrom thenext- statecolumns ofAand Band expressed insum-of-minle rmsformas

A(,

+

I) = D,(A.B.x) = ~(J.5.7) B(/ · 1)

=

^{D. (A. B.x)}

=

~(1.5.7)

y(A.B..r] = ~(6.7)

228 Chapter5 Syn chronou sSeq uentiallogic

Table5.11

Stot~ Tab~for SeqlRnuDtr«tOf

Pre sent Next

State Input State Output

A

• ^•

^A

• ^r

0 0 0 0 0 0

0 0 I 0 I 0

0

,

0 0 0 0

0

,

I

,

_{0 0}

I 0 0 0 0 0

I 0 I I I 0

I

,

0 0 0

,

I

,

I I I

,

whereA and Bare thepresent -statevaluesoffiip- flopsAandB.xistheinput.andD_Aand DB are the inpu tequation s.Themintennsforoutputyarcobtained from the outputcolumn in the state table.

The Booleanequatio ns are simplifiedbymeans ofthemapsplott ed in Fig,5.28.Thesim- plified equationsare

D_A = Ax

+

Bx D8=Ax +B'x

Y = AB

TIle advantageof designingwithDflip-flopsisthai the Boolean equations.describing thein- puistotheflip-flopscan beobtained directlyfrom thestale table.Softwaretoolsautomatically inferand selectthef)-typeflip-flopfromaproperlywritten HOL model.Theschematicof the seque ntial circuitisdrawn inFig.5.29.

B

,

, - 148

B

,

A

..

00 ^"01 ^" II

^-,

10

0

A l' -. .. _{I f , , i}

B

,

D, - A.r+B'x

B

• ^.

A

..

00 01 II 10

I I I I ..

^"

0

Al' ^{" i :i ~.} ..

~.,&

. ~

B

•

B

A ..

00 ^"01 ^" II ^" 10

0

,

A I,

^"

1 ( '

^{l"r'=.,jJI :'; "}

,

fiGURE 5.28

Mapsforseq ue nce detector

SectionS.8 Design Procedure 229

,

~

_~

J , 0

IS

l£4Z ^I

J )§

I

I

Ciock

T

A

8

B'

)

FIGURE5.29

logic diagr am ofseq uence detector