Introduction to Sequential Logic Circuits

Chapter 5

Synchro no us S eq ue nt ial Logic

5 . 1 INTRODUC TION

'Thedigitalcircuits COll,idertdihusfar have beencombination al: thaIi...theOOlpuban=enurely tkpcndcfII on thecurrent lnpcrs.Ahhougheverydigital")'~cmi'\likely to have\011lCcom bi- nationa lcircuit...fllO!r-l ,)'"Ic m ..encou ntered in practice al..o include Mengeclcmcnh. which require thatthe'\Y!iolcmbedescribedinterm..ofstqllC'miol l oR;C._Fi~I.wereed10undc...and whatdislingui\ hc:'\~ucnlial 1ogkfrom combinationallogic.

5 . 2 S EQU ENTI AL C IRC U IT S

A blockdiagramofa ,..:quentinl cirruiti..sbownin FiB.5.1.Itcons! ..t of.cornbinauonalcir- cuur o whkh_M{KlI~Cclement..areCOflna:1a.1(0fonnllfeedback

pam.

1llC!>wrag eeleme ntsart

device scapableof!>Ioo ng binary information.The binaryinformationstOf't'lJin Ihe"oCelerrems al any giventime:define..thestate ofthC'sequentialcireuitalthattime.The sequential circuit receives binary informa tion (rom externalinput!> Ihut.logethcr withthe present \laleofthe

Inpun

(·umt!\IUlI""".1

r-r-

^OfCUl1 _clemeni.^MC ID... ' "

-

Ou/pun

182

fiGURE. 5.1

Blo<k diagram of'~quentlaldttult

Section5.2 Sequential Circuits 183

storageelements. determinethe binary valueof the outputs.These externalinputsalsodeter- minethe conditionfor changing the state in the storageelements. Theblock diagramdemon- straresthattheoutputs ina sequentialcircuit are afunctionnotonly of theinputs, butalsoof the present stateofthe storageelements. The next stateof the storageelementsis alsoafunc- tion of externalinputsand thepresent state. Thus,asequentialcirc uitis specified byatime sequenceof inputs,outputs, andinternal states. Incontrast. theoutputs ofcombinational logic depend onlyonthe present valuesofthe input s.

There aret....-cmaintypes ofsequentialcircuits,and their classification is a functionof the timingof their signals.Asynchronoussequentialcircuitisa system whose behaviorcan be defined from theknowledge ofits signalsat discreteinstant s oftime.Thebehavior of an(lS)"I-

chron oussequentialcircuit dependsuponthe inp utsignetsat any instantof timeandthe order inwhichtheinputs change,The storage elements commonly usedinasynchronous sequentia l circuits are time-delay devices.The storagecapability ofatime-delaydevicevarieswith the timeittakes for the signal to propagatethrough the device.Inpractice, the internal propaga- tiondelay of logic gates is ofsufficient duration toproducethe neededdelay, so thatactual delay unitsmaynotbenecessary.In gate-typeasynchronous systems, the storage clement s consist oflogic gales whosepropagationdelayprovides thereq uiredstorage . Thus,an asynchronous sequential circuitmayberegarded as a combinationalcircuit with feedback.Because of thefeed- back among logic gates, an asynchronous seque ntialcircuit may becomeunstable at times.

The instabilityproblemimposes manydifficultiesonthedesigner.Asynchronous sequentialcir- cuitsare presentedinChapter 9.

Asynchronoussequentialcircuitemployssignals thataffectthe storageelementsat onlydis- creteinstantsoftime. Synchro nization is achieved by atimingdevice called adock Rt'Ilt'ru- tor,whichprovidesa clocksignal havingthe form of a periodictrainofclockpulses.The clock signal is commonly denotedby the identifiersclockandelk.Theclockpulsesaredistributed throughoutthesystemin sucha waythat storageelements are affectedonly withthearrivalof each pulse.Inpractice. theclock pulses determine when computational activity will occur within the circuit,andothersignals(external inputs and otherwise)determinewhatchanges will takeplace affectingthe storage elements andtheoutputs.For example,a circuit that istoadd andstore two binary numberswouldcompute theirsum fromthevalues ofthe numbersand store the sumatthe occurrenceofa clockpulse.Synchrono ussequentialcircuits thatuse clock pulses to controlstorageelementsare calledclockedsequential circuitsand arethe type most frequentlyencountered in practice.They are calledsynchronouscircuitsbecause the acti vity within the circuitand theresulting updatingofstored values is synchronized to the occurrence ofclockpulses. The designof'sy nchronouscircuitsisfea sible because they seldom manifest instability problemsand theirtiming iseasilybroken down into independent discrete steps, each of which canbe consideredseparately.

Thestorage clements(memory) usedinclocked sequentialcircuits arecalledflip-flops.A flip-flop is a binarystorage device capableofstoringone bitof information. In astable state, theoutputofanip-flop iseither0or I.Aseq uentialcircu it may usemanyflip-flopstostore as many bits as necessary.The blockdiagram ofa synchronous clocked seq uentialcircuitis shown inFig.5.2.The outputs areformed bya combinational logicfunctionoftheinputs10 thecircuitor the valuesstored in the flip-flops(orboth) . The valuethat isstoredinaflip-flop when the clockpulseoccursis also determined bythe inputstothe circuit or the values presently

184 Chap ter 5 Synchron ousSequenUalloglc

Inpull

Comtoinalio...1

...

^{tl'CUIl FlIP.fIor'}

I -

Clock pultn

I

Outpull

IN TImillJ dilarlm ofclockpubn FIGURE.5.2

Synchronousdod.ed SflIuen Ualcircuit

storedin theflip-flop lorboth).Thenew value isstored(i.e.•theflip-flop isupdated)whena pulse oftheclock si, n.tl occurs.Prior10 theoccurrenceof theclockpulse.thecombinational logicformingthenext value of theflop-flopmusthave reacheda5.tIbievalue.Consequently, thespeedat whichthecombinational logic circuitsoperateiscritical.Iftheclock(syochro- nizing)pulsesarriveata regularinterval,a, shownin thetimingdiagraminFig.S.2.thecom- binationallogicmust respond10 a changeinthestaleof the flip-flop intimetobeupdated before thenextpulseJ.IT'ives.Propagationdelaysplayanimportantrole indeterminingthe minimuminterval betweenclock pulsesthat willallowthecircuit to operatecorrectly.The stateof theflip-flop!'canchange only during a dock rubelran, ition- fOf example.whenthe valueofthedock signalschanges from0toI.Whena clockpulseisnot ective.thefeedback loop between the valuesroredin the flip-flop and thevalueformed at the inpul totheflip-flop iseffectlvely brokenteceuse the flip-flop outputscannotchangeeveniftheoutputs ofthe combinationalcircuitdrivingtheirinpulschangeinvalue.Thus.the transitionfrom onestale tothe next occursonl) atpredeterminedintervalsdictatedby theclockpul5.Ct.

5 . 3 ST O RAGE ElEM ENTS : LATCHES

Astorageelemersinadigital circuitcan maintainabinarysUICindefinitely(as longaspower isdeliveredtothecircuit).untildirectedby an input signaltoswitchstates.Themajordiffer- encesamongvarioustypesofstorage clementsarein thenumber of inputsthey_~\loCsSand in themannerin whichtheinpulsaffectthebinary stale.$ro'Og('('/('m('nUtMIoperate "';,h s/gllfll1('1'('/s(rolhu lhansignallronsitionJ)arr rrfrrndtoaslalchu :those controlledbJa clocktransitionorrflip-flops.Latches arcsaid tobelevelsensitive de\'k a :flip-llop5.arcedge- sensitivedc\'ilXS.,lbc twoI)'PCSofstorage elementsarerelatedbecauselatchc.arethebeic circuitsfromwhichallIlip-flopsareconstructed.Althoughlatches arcuseful (or storing binary Informationand

roe

thede ignof asynchronou sequential circuits(!ICCSection9.3).theyarc

SR

Latch

Sect ion5.3 Storage Elem en t s:lat ches 18S

not practicalforuseinsynchronousseq uentialcircuits. Because theyare the buildingblocks offlip-flops. however.we willconsider thefundamental storage mechanismusedinlatchesbe- foreconsidering flip-flopsinthe nextsection.

TheSRlatchis a circuit withtwo cross-coupled NORgales or two cross-coupled NANDgates.

andtwoinputs labeledSforsetandRfor reset.The SRlatchconstructed with two cross- coupled NORgatesis shownin Fig.5.3.Thelatchhastwouseful states. WhenoutputQ "" I

andQ' ""O.the latch is said to bein thesetstate.WhenQ""0 andQ' ""1.it isin thereset

state.OutputsQandQ'are normallythecomplementof each other.However.when bothin- putsare equalto I at the same time,a condition in which bothoutputsareequalto0(rather than be mutually complementary)occurs.Ifbothinputs are thenswitched to 0simultaneous- ly, thedevicewill enter an unpredictableor undefinedstate or a metastablestate.Consequently, in practical applications.setting both inputsto 1isforbidden .

Under normalcondition s.bothinp uts of the latchremain at 0 unlessthe statehasto be changed. Theapplication ofamomentary I to the S inputcauses the latchto go to thesetstate.

The 5inputmustgo back to0 beforeany other changes takeplace,inordertoavoidtheoc- currenceofan undefined nextstatethat resultsfrom the forbidden inputcondition. As shown inthe functiontableof Fig.5.3(b),two inputconditionscause the circuit tobein thesetstate.

Thefirst condition(S ""1.R "" 0)isthe action that mustbe taken by inputStobringthe cir- cuit10thesetstale.Removing the activeinputfromSleavesthecircuit in thesame state.After bothinputs returntoO.it isthen possibletoshift to the reset state by momentary applyinga 1 totheR input. The 1 canthen beremoved fromR,whereupon thecircuitremainsin the reset state. Thus.when both inputs S andRare equalto0,the latchcanbe ineither theset or thereset state. dependingon which input wasmostrecently a1.

If a1isappliedtoboth theSandRinputs ofthelatch.both outputsgotoO.Thisactionpro- duces an undefinednextstate. becausethestate thatresults from theinput transitions depends on theorder in whichtheyreturn toO.Italso violatesthe requirement thatoutputsbe the com- plementofeach other.In normal operation.thiscondition is avoided bymaking surethat1's arenot applied tobothinputssimultaneously.

The SRlatch with two cross-coupled NANDgatesis shown in Fig.5.4.Itoperates with both inputsnormallyat1.unlessthe stateof the latch hasto bechanged .Theapplicati on of 0

:JL

^R(reset)

--ff:Y 4--

S(set)- - L../

(a)Logic diagram

S ^{R Q Q'}

Q 1 0 1 0

0 0 ¹ 0 (afterS=l,R-O) 0 1 0 1

0 0 0 1 (aIterS-O.R-I)

Q' 1 1 0

o

(forbidden)

(b)Function table FIGUR£ S.3

SRlatch with NOR gates

S R 00>

I 0 0 I

I I 0 I (. hn S.I.R. OI

0 I I 0

I I I o (.f'ln S-O.R. n

0 0 I _IC'~)

(b)Full(t ioatable fIGURl5.4

S.a.tm

with NAND ,.Iel

10theSinputcausesoutput Qto'010I.putt in, the latchinthe~Male.When the5input,oe'l hackto I.thecircuitremainsin thesetstate.Afterbothinput~10 backto I.weart'allowed to changethe Mateoftbe lalchbyrlucinga 0in theRinput.Thlsecuoncauseslhe circuntogo tothereset state aoo Maythere even after bolhinput'return to I.Thecondition thati' fOfbid- den forthe NAND latch i~bothinputsbeingequal to O atthe~1l\C'time.an inputcombination that"hOuldbeavoided.

Incomparingthel'ASD withlhcNORlatch.notethat theinpul signal\ fortheNANDre- quirelhcromrkmmtt.f too..e valuew.used fortheNORlatch.8cao\ClhcNA,.'Olatch requil't\

a 0lii, naI tochange' it, stale.iti~somenmes referred10a, anS'R'lalch.11M:prirtlC'l(or.^§OO1C'.

li~banoverthckllcn)dcr.ignate lhcfaC1thattheinputsmu~bein thC'ircompkmcnl form 10.ronle thecircu it.

11M:opnationof theba\kSRlatchcanbemodified bypC'Ovidins: anadditiofu] input~.­

nalthat dc1cnninn(c',"lro b)t4'h nlthe!iWeofthe latch canbecb3n~.AnSRlalch""'ilh a controlinput i"!ohowninFi•..5.5.Itron\i\lSoh hcba.,k SRlalchandIWOaddittonalNAND ialC\.1bt:controlinpu lEnaC1Sa" anmabI, s1[1:nal fortheocher two inputs.1bcoutputsofthe NAND,ale, -.layattheloBic·1 levelas

Ion' .'li

^{theenable 'ignal}f'C'TtWns atO.Thi,i lhcqui- C'\«IIIcondilion fortheSRtarcb.wbenlhcenable' inpution10 I.information fromlhcSor Rinpuli~allowedto alT«tthelatch.The!IoC1.starei\ru chn.!withS - I.R - O. and En • I tecn ve-highena bledt.Tochange to the' reset state. the input~ mU:\1be: S - O.R• I. and

s

Fn

R

0

Ffl S R Nut...re of (J

0 X X Sl)dl.n ,e I 0 0 NI),h. nle I 0 I Q.O:.~I"'.Ie I I 0 O· I:w l'....e 0> _{I I I} Indetenn in8le

H'If..mctiollt.No:

"GUll5.5

Sla.tch wtIh controfinput

Section 5.3 Storage Elements:latches 187

D

En D NextslateofQ

E,

---+---+ o

_X

1 0

1 1

Nochange

Q'"0;resetstate

Q= 1;setstate

FIGURE 5.6 D latch

(a)Logic diagram (b) Functiontable

En == I.In either case.whenEnreturnsto0,thecircuit remainsin itscurrentstate. The con- trolinput disablesthecircuitbyapplying0 toEn.sothatthe stateof theoutput doesnotchange regardlessofthe valuesofSandR.Moreover.whenEn == Iand both the SandRinputsare equaltoO.thestate of the circuitdoesnot change.Thesecond itionsare listed in thefunction tableaccompanying thediagram.

An indeterminateconditionoccurswhen all threeinputsare equalto I.Thisconditionplaces O'son both inputsofthebasicSRlatch,whichputsitintheundefin edstate .When the enable input goesbacktoO.one cannot conclusively determinethenextstate.because it dependson whether theSorRinputgoesto 0 first.Thisindeterminate conditionmakesthiscircuitdiffi- culttomanage.and itis seldom usedinpractice.Nevertheless.it isan importantcircuit because other useful latchesandflip-flopsareconstructedfrom it.

o Latc .h (Tra nspare nt Latch)

Onewaytoeliminate the undesirablecond itionof theindeterminatestate intheSR latchisto ensurethatinputsS andRareneverequal to Iatthe sametime.Thisisdone intheDlatch, shown in Fig. 5.6.Thislatchhas only twoinputs:D (data)andEn(enable). TheDinput goe s directly tothe Sinput.and its complementisappliedtotheRinput.Aslong as theenable input isat0,thecross-coupledSRlatchhasbothinputsatthe I leveland thecircuit cannotchange state regardlessof the valueofD.TheDinputis sampledwhenEn == I.IfD == I,theQout- putgoesto I.placing thecircuitin thesetstate.IfD= O.outputQgoestoO.placingthecir- cuitintheresetstate.

TheD latchreceivesthatdesignation from itsability toholddatain itsinternalstorage.It is suitedfor use as atemporary storageforbinary informationbetween aunit and itsenviron- ment Thebinaryinformation present at the datainputof the D latchistransferredtotheQout- put when theenableinput is asserted. Theoutput follows changesin the datainputaslong as the enable inputisasserted.Thissituation providesapath frominputD10 theoutput.andfor thisreason.the circuit isoftencalledatransparentlatch.When the enable input signal is de- asserted.the binaryinformation thatwaspresentatthe data inputatthetime thetransitionoc- curred isretained(i.e..stored)at theQoutput until the enableinput isassened again.Notethat

188 Chapter S SynchronousSequential Logic

- - js -~., - - jv

- --l R

,.

fiGURE 5.7

Graphic symbols for latches

-~ R

r R o

aninverrercoctdbe pta..redat theenable Inpcr.Then. depending onthephysical clrcvit.theex- temalenabling~ignalwill bea valueof0(active low)or I(active high).

Thegraphicsymhol ~fortheverioeslatchesareshowninFig.5.7.Alatchisdesignatedby arectangularblock withinputs onthe Icftand OUlpub ontheright.Oneoctpetdesignalesthe oormaloutput.andt~other(withthebubbledcsiBnation) desiBnalC's thccomplementOUlput.

The graphicsymbolfortheSR latchhasinputsSandRindicatedinsidethe block.IntheCMe

ofaNANDgDtC latch.bobbles areaddedtotheinputs10 indicatethai setting andrelloCuin, occurwitha logic-osignal.Thegraphicsymbol for the0 latchhasinput D andEnindicat ed insidethe block.

5. 4 5TORAGE ElEM ENT5 : Fl IP ·FlOP5

'Thestareofalatchornip-flopis swilched by "changein the controlinputThis momentary change iscalleda'ri8~('r.andthetransitionitcauses h said totrip crthe flip-flop.The0 latch wilhpulsesinitscontrolinput is n.'Cntiallyaflip-flopthat istri"~everytimethepulse goes10thelogic-Ilevel.Aslong a the pulseinput remains at thislevel.any changes inthe datainput willchangelhe outputandthestateof the latch.

Asseenfrom thebhlCkdiagram of Fig.

5.2.

asequentialcircuithas afm!bockpathfromthe output\ofthe_flip-flop~10theinputofthecombinational circuit.Consequently.theinputsofthe flip-flopsarederived inpanfromtheoutpubofthesame andothttflip-l1op5.whenlatches arc used forthe_~torageelements, aser ioc difficulty arisc!'>.TIlestarelnUl!iitiom o(thelalches st3l1

1'1soona.'lthedockpulsechangestothelogic-I level.The new stateofalatch appears atthe outputwhilethepulseisstillactive.Thisoutputis connectedtothe inputs ofthelarcbes through thecombinationalcircuu.Htheinputs applied 10thelatcbes change whiletheclockpulsei 5IilI atthelogic-I level.thelatches will respond10newval~sandanewoutputslalemayoccur.TI1C' m ultis an unpredictable situation.sincethestateofthelatchesmaykeepchanJingfor aslong asthe dockpulse slay!'>attheactivelevel. Because ofthisunrehableoperation.theoutputofa latch cannotbeapplied directly orthrough combinalional logic to the inputofthesame or an- other latchwhen allth~ latcheslU'l:'triggeredby a common dockMJUI'CC'.

flip-flopcircuits are con5UUC1C'd insuch away a\tomake them operate properlywhen they arepanof a5C'q~ntialcircuit that employs a commondock.Tbe problem withthelatch isthai it respondsto a changeintheIn'('1ofaclockpulse.As shown inFig.j.8(a). aposiuve level responseinthe enable inpulallowschangC' inIhcoutput whentheDinpulChaniC5 whilelhe

Section 5.4 Storage Elem ents:Flip-Flop s 189

(a)Respo nsetopositivelevel

(b) Positive-edgeresponse

(e)Negative-edgeresponse

FIGURE5.8

Clock response In latch and flip-flop

clock pulsestays atlogic I.The keyto theproper operationof a flip-flop isto triggerit only duringasignaltransition.Thiscan be accomplishedby eliminating the feedback paththat is inherentinthe operationof the sequentialcircuit using latches.Aclockpulsegoes through tWOtransitions:from0 to Iand thereturn from 1toO.As showninFig.5.8.the positiveIran- sitionisdefined asthe positiveedge andthenegative transition asthe negative edge.There are two waysthatalatchcanbemodified to form a flip-flop.One wayistoemploytwo latches in aspecialconfigurationthat isolatesthe outputof theflip-flop andpreventsit frombeing af- fected whiletheinput to the flip-flo pischanging.Another wayistoproduce a flip-flopthat triggersonlyduringasignal transition(from 0 to Ior from 1100)of thesynchronizingsignal (clock)andisdisabledduringthe rest of the clock pulse.We will now proceedtoshowtheim- plementationof both typesof flip-flops.

Edge-Triggered

0

F lip-Flop

Theconstruction of a D flip-flop with two D latchesand an inverteris shown in Fig. 5.9. The firstlatchiscalledthe masterand the second theslave. The circuitsamplestheDinputandchanges itsoutputQonly atthe negative edge ofthesynchronizing orcontrolling clock(designated as

Q

D- - - I

y

elk_----J~_ _-D~

_ _

^---1

fiGURE 5.9

Ma ste r-slaveDfltp-tlop

190 Chapter's 'synchronousSequential Logic

C/~).When lheclucki'O.theoutputoftheinnnc rillI.Theslavelatch h enabled.and it!'> out-

rut

Qi~cquullOthem;l,l er output

r.

Themasterlatchi,L1i:<.ablcd because CU • O.When lhe inpulpulsechangesIIIthe logic-! level.tbedata from theexternalDinputarctransferred10

the ma..ter.The slave.however.i..disabled a."longa.-.theclock.remain,attheIlevel.because ih_,naM~inpulj,equaltoO.Anychange in theinpulchangelllhcmasteroutput011r. bUIcan-

IKJIaffecttbc ...^101\'('output.Whentheclodpubererum-to O.thcmasterill_L1i~blcdandi!'>iso- lated from the /)input. Atthe:<.arnelime.the ..lavei..enabledand thevalueof

r

^isrran..ferrcd 10(heoutputof the Oip·OopatQ.lllU!l.achange intheoutputofthenip-Oopcanbe triggered unly by aoo duringtherran..itionof theclod from) 10O.

The behaviorofthe master-..laveIlip-Il opjU!'>1described dictates thai(lI theoutputmay changeonly on\,·c.121,. Ch,IO!!Cin theOOlputislrin elT'dI'lythencBati H~edgeof thedud..and 1.'1thechange may occuronlyduringtheclock's ncgauvelevel.The valuethatill prodoccd011

theoutputofthe Ilip-ftop b. thevaluethatwa!'>stored in themacer..rage iml1ll.-diaICI)·before thenegauveedgeoccurred.IIi..alsopOlisibletodesignlhecircuitMJthatlhcfllp-Ilopoctpcr changes onthe positiveedge of theclock.Thishappen..inanip-Oopthatha!'> ana&Jitinna!in- verierbetweenlheCII. terminaland thejurcuonbetween theotherinverterandinput£11oftbe ma..tcrlatch.Sucha Ihp-Ilopi..triggeredwith a negative pol"",1iOth.dlhe: IlCgath'c edge oflhe dockaffC'C1"themasterandthepositiveedgeaffC('hthe slaveand theoutputterminal.

Anothcrconsrrucuon ofanedge-mggered0 Oip·nupU"'lithreeSRlatchc!>av shown in Fig.5.10.TwolalChc"respond10lhe: external0 (daralandCIA (dock)inpuh.The thirdlalch provides the:UUlPUh flitthe: Ittp-Ilop.The:SandRinpul~ofthe octpetlatchare maintained011

the logic-I levelwhenClk - O.Thtscausestheoutput10remain in itspre1iCntstate.(npuc0

• ,

n - - - - if---1._ ./

FtGURf S,10

D-typeposlltve-edge-trigger~flip-flop

- --jll

Section SA Stor age Eleme nts:Flip-Flops 191

II

FIGURE 5.1 1

Graphk symbolf~edge-trlggeredDnip-flop

maybeequalto0 or I.IfD "" 0when C/kbecomes I. Rchanges toO.This causes thenip-

floptogototheresetstate.makingQ ""O.If thereisa cha ngeintheDinput whileClk

=

^I,

termin al R remainsat 0 becauseQis0,Thus.theflip-flopislock edoutandisunrespo nsiveto furtherchangesin theinpu t.Whenthe clock returnstoO.Rgoesto I,placin gtheoutput hitch in the quiescentcondition witho ut changing the output.Similarly,ifD = I when Clk goes from010 I.Schangesto 0,Thiscausesthe circuit togotothesetstate,makin gQ "" I.Any changein DwhileClk ... I doesnotaffect the outp ut.

Insum. whenthe input clock intheposidve-e dge-mggeredflip-flopmalesa positiveIran-

siuon.^{the valueofD istransferredtoQ.A negative} tran sitionof theclock(i.e.•from Ito0) doe snotaffecttheoutput.nor istheoutputaffec tedby changesinDwhenClkisin thesteady l08 ic-1 levelor the logfc-nlevel.Hence. thistypeof flip-floprespondstothetransition from 010 Iand nothingelse.

Thetimi ngof the respo nseofaflip-flopto inputdata and10 theclock mustbetake ninto considerationwhenoneisu..ingedge-triggeredflip-flops.There is a minimu m lime calledthe setuo time duringwhich theDinputmustbemaintai nedat aconstantvalue prior to theoc- currenc eoftheclock transit ion.Similarly. thereis a minimumtime calledthe holdtimedur- ingwhichtheDinputmust DOl change,iftertheapplicationofthepositive transition ofthe clod... Thepropagationdelaylime ofthe nip-flopis definedasthe intervalbetween the triggeredge andthestabilization oftheoutput10 a newstate.These andotherparameters are specifiedin manufac turers'databooksfor specificlogicfamilies.

Thegraphicsymbolfor the edge-trigg eredD flip-flopis shown inFig.5.11.Itis sim ilarto the symbolused forthe[)latch,except forthearrowheadlike symbolinfront oftheletterClk, designatingadynamicinput.Thedynamicindicatordenotesthefactthattheflip-flop responds totheedge transitionoftheclock.A bubble outsidetheblockadjacenttothe dynam ic indica- tordesignatesanegativeedg efor triggeringthecircuit. Theabsenceofabubbledesignatesa positive-edgeresponse .

Other Flip-Flop.

Verylarge-scale integ rationcircuitscontain thousands ofgateswithin onepackage.Circuit.. are constructed byinterconnectingthevariousgatestoprovideadigital system,Each flip-flopiscon- structed from aninterco nnectionofgales.The mosteconomicalandefficient flip-flop con- structedinthismanneristheedge-triggeredDflip-flop.becauseit requiresthesmallestnumber

192 ChapterS SynchronousSeque ntiallogic

/ - - - ---;- /

K - -D- --f" --'"

flC.URI5,U

IK

nip-flop

I-t-+-Q

~I 'I

- --1 / ----1 t> m

- l.:.. • . J -

ofgates.Other types01'nip-flop!'can beron~r\ldC'dbyu~ingtheDnip-flopIlOdexternallogic.

Twonip-flop-.lee..widelyusedinthe designof digitalsystemsaretheJKIlOdTnip-flops.

Thereare threeoperationsthat canbe:performedwithanip-flop:Sc:1it toI.resetit toO.^Of complementil~output. Wilhonlya single input.the0 nip-nopcansetor reset the:output. de- pending onthevalue^(11"the:0 inputimmediately beforethe:clocktransition.Synchronizedby aclock.signal,lhe:JKnip-flop ha'ltwoinputsandperformsall threeoperation".Thecircuitdi- agramofaJKnip-flop constructed witha0 nip-flopandgates is showninFig.S,12(a).The Jinpul^setsthe:Ilip-Ilop10 I,the:Kinputresetsit toO.and whenbothinputsan:enabled. the OUlpul^j"complerremed.This canbe:verified byinvC'stigatingthecircuitapplied tothe:^Dinput:

D - IQ'

+

K'Q

WhenJ • IandK - O.0 • Q'

+

Q• I.sothe11C1I.tclockedgesets the:output 10I.When J - 0 uOOK • I,0 ""O.sothe:nextclock.edgereloctstheoutputtoO.Whenbod1J • K • I andD • Q' ,thene1l.1dock edgerompkmen~theoutput.WhenbothJ • K • 0aoo0 • Q. the:clock edgeleavestheoutput unchanged.The graphic symbol fortheJKflip-flopisshown in Fig.S.12(b),Itis sirnilar tothegraphicsymbolof the:Dflip-flop.except thatnowthe:in- putsaremarkedJandK.

The: T (toggle)flip·l1opisacomplemenungflip-flopandcan beobtainedfrumaJK flip- flop when inputs J and K are tied rc gerber. This is shown in Fig. S,13(a), When T • 0(J • K - 0).aclockedgedoesnoc changetheoutput.When T - I(J • K - I).

aclock edge complementstheOUlput.Thecomplementingflip-flop isusefulfor lk"iBningbi- nary counters

TheTflip-nopcanheconstructedwithaDIlip-Ilopand anexclustve-Oggatea.\ sbown in

Fig.5.13Ib).TheexpressionfOftheDinputiv .

D -TeQ -TQ' +T'Q

When T - O.D - Qandtherei~nochanBcintheoutput.WhenT - I.D • Q'and theout- putcomplements,The graphicsymbolforthisflip-flophasaTiymbolinthe:input

Section 5.4 Storage Elements:Flip-Flops 193

T-'--1J elk

K

{a)FromJKflip-flop

fiGURE. 5.1J Tflip-flo p

Characteristic Tables

T

11

"

"

(b)FromD flip-fl op

T

- - jl>C lk

(c)Graphic symbol

Acharacteristic tabledefinesthelogicalproperti es of a flip-flop by describingitsoperation in tabularform.The characteristictablesof threetypes offlip-flopsare presentedin Table5.1.

They definethenextstate (i.e.. thestate thatresultsfromaclocktransition) as afunction of theinputs and the presentstate.Q<r)refers tothepresent state(i.e.•thestate present priorto the applicationof a clockedge).Q(t

+

I)isthe nextstateone clockperiod later. Notethatthe clock edge input isnotincluded inthecharacteristictable. butisimplied10occur between timestandI

+

I.Thus.Q(t)denotesthe stateofthe flip-flopimmediatelybeforetheclock edge.

andQ(t + J)denotes thestate that resultsfrom the clock transition .

The characteristictable for thelKflip-flop shows thatthenext state isequalto the present state when inputs 1 and K are both eq ual to O. This condition can be expressed as Q(t

+

I) = Q(t).indicating that theclock produces no changeofstate.WhenK = Iand

Ta b le 5.1

Flip-FlopCharac teris ticTables

JKFlip-Flop

J ^{K Q(t} + 1)

0 0

e»

^{No change}

0 I 0 Reset

I 0 I So<

I I Q'(') ^Complement

DFlip-Flop T Flip-Flop

0 Q(t + 1) T Q(t + 1)

0 0 Reset 0 Q(t) No change

I I So< I Q'« ) ^Complement

194 Chapter S Synchronou$Sequential logic

J - O.thedock reM'I!llhe nip-nul'andQ(I+ I) - u.wnhJ - IandK - O.theniP-tlOf

~I~andQ(1 ... I) "" I.When hothJ and Kareequal to I.the next~tate,"h.m~e!ltothe:rom

plemenrof'thepeesem state,arransiuonHUllcanbeexpressed asQ(t ... t) - Q'(I).

Thef)Ckt~t3teofa0 nip-flopisdepende ntonlyon the0 inpu tandis independentoflhc

prt~ntstate.This canbeell.~!\Cda'iQ( t

+

I) • D.IImeansthallhenCII.l-!.latevalue isequa tothe valueofD.Notethatthe:0 nip-fl op doesnotha ve a"no-chan ge"condition.Sucha con- ditioncanbeaccomplbbedeitherby disabl ingthe dod or byoperatingtheclock byhavini theoutputofthe flip-flopconnected intolhe () inpu t.Eithermethodeffectivelycirculates ttl<

OUlputof lhcfhp-Ilop whe nthe:S1aleoftheflip- flupmu..t remainuncha nged.

ThechardC1cri~ictableoftheTtlip-l1op has onlytwo(,'{n1ition..:WhenT • O.theclockedge doesnot cbengcthest.ue:whenT - I,thedodedgecom plemenL'ithe!'>lateoftheIlip-Ilop.

C haract eris ti c Equations

Thelogicalpn"enic-of3 Ilip-Ilop,a'ic.k"MTibcdin the charoK.'1cri..tictable.canbe:ell.prn.iedal·

gcbreicallywith acharal,.1cri~icequation.fQrthe0 Oip-lK'P.webavethechar.tctcri'-liceqoatton Q(/ + I) -/)

whichslatesthat thc=next!ltateof thc:outputwillbeequaltothe valueof input 0 in the _prC'~' entMale.Thecharacteristicequation (Of'theJKIlip-Itopcanbederived fromthecharecte ris- tictable or fromthecircuitof Fig.S.12.Weobtain

Q(/ + ^{1) -} JQ' + K'Q

whereQi~the value(Ifthe nip-nopoutput prior tothe appliCitinnof a dock edge.Thechar-

ec r er isnc

equationfortheTflip-flop_i~ohcaincd fromthe circuitof Fig.5.13: Q(/ + 1) - T(IIQ - TQ' + T'Q

Direct Inputs

SomeIhp-flopshav e iL\Ynchronou...inptlts mat art'used 10

f orce

thenip- nop to a panicul ar stateindepende ntly oftheclock.Theinpo l thal_!ICt~the nip-flop10 t h calledpm t'lorJilt'''l set.Theinput that cleanthe Iltp-nop toOiscalledclearordirectIt'st".Whenpoweristurned 00 inadi~ital system.the state of the nip-nopsisunknown.Thedirect input~areu~fulfor bringingall nip-flu!", mIhc=system10IIknownManing..late priortothe clockedopera tion.

A po...itive-etl¥C'"tri~~rtdDnip-llop withecuve- jowa..ynchnKkllJ" m.et is~1linFig.S.14.

Thecircuitdiagramis lhesameasthe one in Rg..5.10.except for the additionalresetinpulcon- recuonstothreeNAr-;Dgales.Whentheresetinpuli~().itforcesoutpu tQ'to Slay011I.which.

in tum. clea n output(!10O.lhu~re~uingthe Ilip-flop.Twootherconnections fromthem<1

inputensurethaithe.\ inpu tofthe thirdSRlatc hstay~atlogic Iwhile lhereset input is at O.

reganl le!>\of the vallk."sof0 and Clk.

Thegraphicsymbol for the0 nip-flop withadirttl resetha...IllIlkkIitional inpul

maned

with R.Tbebubb lealoo gthe inputindicatesthatthe fC!>C1is ecuve at the 1000ic.Qlevel.Hip-Flops withIIdirec t.-.elU\Cthe symbolSfor rbeasynchnmou sSCiinput.

Thefunctiontablespecifiesthe operalion of thecircun.WhenR• O.theOIJlputi..reset10O. This~tateis Independentofthe values of0 Of'C/~ .Normalclockoperatio ncanproceedonly

Sect ion 5.5 AnalysisofClocked Seq uentialCircuits 195

Clock

Rt''; f l - -- ' --'

fa) Circ uitdiagram

Dura [)

Clock

e lk

R

Reset

I

1--0 1>-- 0 '

R CfkD Q Q'

o

X X 0 I

o t o o I

o

t I I 0 (h)Graphic symbol

FIGURE 5.14

Dflip-flopwit hasynch ro no us re set

(b)Functiontable

after the resetinput goestologic I.The clockatelkis shown with an upward arrowtoindi- cate that theflip-floptriggersonthe positive edge of theclock.The value inDistransferred toQwithevery positive-edgeclocksignal.providedthatR = I.

5 ,5 ANALY51 5 OF CLOCKED SEQUENTIAL CIRCUIT5

Analysisdescribeswhnta givencircuitwilldo undercertainoperating conditions.Thebe- havior ofaclocked sequentialcircuitisdeterminedfromtheinputs.theoutputs. andthestate ofitsflip-flops.The outputs andthenextstateareboth afunction of the inputsandthe present

196 Chapter 5 Synchronous S~uentlalloglc

stale.The analysis ofUsequennatcircuit comim ofoblainingatableor adiagramforthetime sequenceofinpuI~.outputs.andinternallIalell.Itill,'11M)possible10 writeBooleanexpre sion~

thatdescribelhebehavior ofthe sequentialcircuit,Tbese expressions mustindudctheneces- sarytimesequence.enber direcnyor indirmly,

Alogic diagrami!orecognizedall adocked sequentialcircuit ifit includes nip-flopswith clockinput~.The flip-tlop!imaybe of any type.and the logicdiagrammayormaynotinclude combinationalcircuitgates.In thissection.we introduceanalgebraicrepresentation forspec- ifyinJthenext-statecondition interms oftheprtsc:m slateand inputs.Astate tableandslate diapamarethenpeesenecdtodescribethebehaviorof lher.tquentiaJcircuitAnlXhr:ralgdnicrep- reKnlationismeodcccdfor spccifyi nithelogic diagram of_~nlialcircuits.Examplesare usedtoillustrate thevariousprocedure ,

State Equations

Thebehavior ofaclockedsequential circuitcanbedescri bedalgebraically by meansofstate equations.AJW" 'qUe/lion(also calledatransition,q.klt;Otf)specifiestheIlC'lltstaleas afunc- lionof thcpre\Cnt stall'andinpns.Considn thc sequential circuitr.bowninFig.5.15,11consists

.. I

:::L

^{<,. / 0}

J r -

^{[>n l.}

1

⁰

f- t>

^CIA

C1/1d:

I '

^~

J

e,

I

v

A

A'

8

8'

..

neUR! S.lS

Exampleof~uentlalcircuit

Section S.S Analysisof Clocked Seq uential Circuits 197

of twoDflip-flop sA and B,an inputx andanoutp uty.SincetheDinputofaflip-flopdeter- minesthe valueofthe nextstate(i.e.,the state reached aftertheclock transition),itispossible to write a setof stateequations forthecirc uit:

A(I

+

1) = A(t)x(t)

+

B(I)x (l ) B(I

+

1) = A'(t )x(t )

Astale equation isan algebraicexpression that specifiesthe conditionforaflip-flop state tran- sition. The left side ofthe equation, with{r

+

1).denot esthe next stateof the flip- flopone clock edge later.The rightside ofthe equationis aBooleanexpressionthatspeci fiesthe pres- ent stateand input conditions that makethe nextstateequalto I. Since allthe variables inthe Boo leanexpres sio ns are afunction of the pre sentstate. wecan omi t thedesign ation (t) after each variablefor convenience andcanexpress the stateequations inthemore compact fonn

A(t

+

1) = Ax

+

Bx B(r+ I) = A ' x

The Boolean expr essions for the state equationscanbe derived directl y fro mthe gates tha t formthecomb inationalcircuitpart of the sequentialcircu it.sincethe D values ofthecombi- nationalcirc uit determine the nextstate. Similarly,theprese nt-s tatevalueof the outputcan be expressedalgebraicallyas

)'(1) = [A(I )

+

B(t)Jx' (t)

By removingthe symbol(t)for the presentstate.we obta inthe outputBooleanequatio n:

y

=

^(A

+

^B)x'

Stale Tab le

Thetime sequenceof inputs,outputs,and flip-flop statescan beenumerated inastate table (some- times calledatransitiontable).The state tablefor the circuitofFig.5.15is shown in Table5.2.

Table 5.2

StateTable for the Circuit ofFig.5.75

Present Next

State Input State Output

A 8 x A 8 _Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 1 1 0

1 0 0 0 0 1

1 0 1 1 0 0

1 1 0 0 0 1

1 1 I 1 0 0

198 Chapter S SynchronousSequential logic

Thetable con..i~l~oflour section..labeledpresem _jlrl1~, inpul ,n,,;1_jfjU~, andIIut/ml.The present-stare !oeCtioflshowstbc",Ialelofnip-nop"AandHIIIanygweolimet.Theinpulsec- liongiv~a value of.rfor ecchpossiblepn:!lCntstate.The nnl-litlltesection!>ho,,"~lhe Malell of thenip-fl()p~onc clpckcyclelater,atlimeI

+

I.TheOUlputsectiongivesthevalueof)'al lime1for eachpresent..talcand inpulcoedinon.

ThedcrivlIIiun of11 ,laiClablerequiresliMinBallp'-Miblebinarycombinalion" ofpresent rolalellaoo inputs.Inthl ~ca1OC.\\"ehave ei,hl binarycom binaliom(rom 000 10III.TheRCli' state values are tben"klcmlincdfromthe logicdiagram

t .

^{from lhC'!loIIlIC}equatioevTbc RCIII stareofnip-nop A mu-i5ali~fythe liilateequation

A(r

+

I) - A.t + Bs

Ther\C1I1·slalesectionin the ..laictable undercolumn Aha...three1':10 where the presentstate ofAaoo input,t archillhequal 10 Iorthepresem..laic ofHaodinput.rare bothequalto I. Similarly.the r\C1I1..I.lIIl.."ofItip-IlopHillderivedfromIht.'"laicequeuon

H(/ + I) -A'.t

andi\equal~o I whenlhe present\talcofAi~0and inpulxj"equal 10 I.TheOllipulcolumn illderivedfrom theourputequation

y - Ax' + R.t ·

11lcMaletahlc o(a~"qucnlialdrcuil wilh[J.IYPC nip-noV"ill obtnincdbythesame procedure ollilinedin thepreviou-,example.Ingeneral. asequentialcircuitwithmnip-nos»andninpuh need..2....¹¹rowsinthe statetable.Thebinary numbers from0through 2....^11- Iarc: listed underthepresem-aacandinpsncolumns.Tbcnext-statesectionha~ mcolumns oneforeach nip-flop.Thebinary\'alut'll(orthenextslate arederiveddirecllyfromthestateequations.T1lC' outputsection has as manycolumnsa\ tbetearcoutpu tvariables.liSbinaryvalue is derived fromrbecircuitor fromtbeBooleanfunctioninthe_~memannerasinatruthtable.

Iti\ sometimescoover nenrrocxpre:\.\the ..talctableina slightly differentform having only threesections:present -tate,nextstate.andoutput.'Theinpulconditionsarcenumeratedunder the nnl·slale and outputsections.ThestatetableofTableS.2is repealedinTableS.J in this

!i«OOl.IIorm.

I , .

^eachIlfC\C'lIMale.therearc twopo!-..i~lenutslalCllandocipcrs,depending 00 lhevalueof1M- input.(meform maybepreferable10 thece bcr.dcpcfk1inion theapplication.

T.bleS.3

S«ondFann offM Stofl Tobk

Pr es enl NaxlSlale Outpul SI.le • • 0 • • I • • 0

• •

^I

A

•

^A

•

^A

• r r

0 0 0 0 0 I 0 0

0 I 0 0 I I I 0

I 0 0 0 I 0 I 0

I I 0 0 I 0 I 0

Section 5.5 Analysis of Clocked SequentialCircuit s 199

00

,

.0

',0 ^0/1 ',0

,

1,0

@ - - -"-'-- -(

¹¹

FIGUA£5.16

State diagram of the circuit of Fig.5.15

State Diagram

The informationavailable inastatetablecanberepresentedgra phically intheform ofasuue diagram.In this type ofdiagram.astateis represen tedby acircle.lind the (clock- trigge red) transitionsbetweenstates arcind icatedbydirectedlines connectingthe circles.The slate dia- gramofthe sequentialcircuitofFig.5.15 is showninFig.5.16.The state diagramprovidesthe ....meinfonnation asthestaretableand isobtaineddirectly fromTable 5.2orTable 5.3.The bi- nary numberin..ide eachcircle identifiesthe state ofthe flip-flops.Thedirected line.. are la- beled withtwo binary numbersseparatedbya slash.Theinputvalueduringthe presentstaleis labeledfirst.andthenurnbe...afterthe slashgivestheoutput duringthepresentstalewiththe given input.(Itis importanttorememberthatthebitvaluelistedfortheoutputalong the directedline occursduringthepresentstaleand withtheindicated input.and hasnothingtodowiththetran- sition10the nextstate.)For example.thedirected line from slate001001 islabeled liU.mean- ing thatwhenthe seque ntialcircuit is in thepresentstale00 andtheinputis I.theoutputi..O. After thenextclockcycle.thecircuitgoes 10the nextstate.01.If the inputchanges toO.then the outputbecomes I.buriftheinput remain.. atI. the output"lays atO.This informationi'>ob- tainedfrom thestarediagram alongtheIWOdirected line..emanatingfromthe circlewithstale 01.Adirectedlineconnecting a circlewithitselfindicates tbarnochange ofstate occurs.

Thereisno differencebetweenastate table anda statediagram.exceptinthemannerofrep"

re..entation.Thestatetableiseasier10 derivefromagivenlogicdiagramand thestale equa- tion.Thestate diagram followsdirectlyfromthe:state table.Theslatediagramgives apictorial view of state transitionsand isIhe formmoresuitable forhumaninterpretationofthe circuit's operation. Forexample, the state diagramofFig. 5.16clearlyshowsthat, starting fromstate 00.the outputis0alilongasthe inputstays at I.Thefirst0 input afterastring of I'~gives an outputof Iand transfers the circuitbacktotheinitialslate.00.Themachine representedby thestate diagramacts10detectazerointhebitstream of data.

Flip-Flop Input Equations

Thelogicdiagramof a sequentialcircuitconsists ofnip-flopsandgates.Theinterconnections among thegates(annacombinationalcircuitandmay bespecifiedalgebraicallywith Boolean

200 Cha p ter5 Sync h ro no us Seq ue nt ial lo g ic

expression s.Theknowledge ofthetype of flip-flopsand alist of theBooleanexpression s of thecombinationalcircuit providethe information neededto drawthe logicdiagram ofthese- quentia lcirc uit.The part ofthe combinationalcircuit thatgeneratesexternaloutputs is de- scribed algebraicallybya setofBoolean function scalled output equations.The part ofthe circuit thatgenerates the inputstoflip-flops isdescribed algebraicallybyasetof Booleanfunc- tionscalled flip-flopinputequations(or,sometimes.excitation equations ).We willadoptthe conventionofusingthe flip-flop inputsymbolto denote the inputequationvariableandasub- script to designatethename oftheflip-flop outpu t. For example.thefollowing input equation speci fiesanORgate withinputsxand}'connectedtotheDinputofaflip-flop whose output islabeledwith the symbolQ:

DQ= x + }'

ThesequentialcircuitofFig.5. 15consistsof twoDflip-flopsA andB.aninput.r.andan outputj-, The logicdiagram ofthe circuitcanbe expressed algebraicallywith two flip-flop input equationsand anoutputequation:

D" = Ax + Bx DB= A'x

Y= (A

+

B)x'

Thethreeequations providethe necessaryinformat ionfordrawingthelogic diagram ofthe sequential circuit.The symbolD" specifiesaDflip-floplabeled A.DBspeci fiesa secondD flip-flop labeledB.TheBooleanexpressionsassociated with thesetwo variablesandthe ex- pressionforoutput}' specifythe combinationalcircuitpartofthesequential circuit.

Theflip-flopinput equationsconstitutea convenientalgebraicform forspec ifyingthe logic diagram of asequential circuit. Theyimplythetypeof nip-flopfrom thelettersymbol.and they fullyspecifythe combinationalcircuit thatdrivestheflip-flops.Note that the expressionfor theinput equationforaDflip-flop is identical tothe expressionfor the corresponding stateequa- tion. Thisis becauseof the characteristicequat ionthat equatesthenext slate tothe value ofthe Dinput:Q(t

+

I) = D_Q•

An a lysis with

D

Flip -Flops

Wewillsummarize theprocedure foranalyzinga clockedsequentialcircuitwithDflip-flopsby meansofasimple example. The circuit we wantto analyze is described bythe inputequation

The DA,symbol impli esaDflip-flopwithourputA.The.randy vari ables are the inputsto the circuit.No output equationsaregiven,whichimplies thatthe outp utcomes fromtheoutput of theflip-flop.Thelogic diagramis obtainedfro m theinputequationandisdra...n in Fig.5.17(a).

Thestate tablehasonecolumnforthe presentstate offlip-flopA.twocolumn s forthe two in- puts,andonecolumn forthenextstateof A.Thebinary numbers underAt)'are listedfrom000 through IIIas showninFig.5.17(b).Thenext-state valuesare obtainedfromthestate equation

A(l

+

I) = A$xEl:ly

Section 5.5 Analysisof Clocked SequentialCircu its 201

Present Next

state Inputs state

A ^{, y} A

0

o

0 0

0

o

1 1

.r D_:._, A 0 1 0 1

y 0 1 1 0

1

o

0 1

1

o

1 0

1 1 0 0

Clock 1 1 1 1

(a) Circuitdiagram (b)Statetable

01.10

01,10

(c) State diagram

00.11

FIGURES.17

Sequential circuit with D flip-flop

Theexpressionspecifiesanodd function and isequalto1 when onlyonevariableisIor when all three variablesare1.This isindicated in thecolumn forthe next state ofA.

The circuithas one flip-flopandtwo states. The state diagramconsists of two circles, one foreachstateas shown in Fig.5.17(cl .The present state and theoutput can beeither0 or I,as indicated bythenumber inside thecircles.A slashon thedirectedlinesisnot needed,because there is no outputfroma combinationalcircuit. The two inputscanhavefourpossiblecombi- nationsfor each state. Twoinput combinationsduringeach statetransitionareseparatedby a commatosimplify thenotation.

An a lysis with JK Flip-Flops

A state tableconsis ts of four sect ions: present state,inputs.next state, andoutputs.The firsttwo areobtained by listing all binarycombinations.The outp utsectionis determined from the outputequations. Thenext-statevalues are evaluatedfromthestateequations.For aD-typeflip-flop,thestateequation isthesame astheinputequation.Whenaflip-flop other thantheDtype is used,such aslKorT, it is necess ary torefertothecorrespondingchar- acteristic table or characteristic equation 10 obtainthe next-statevalues.Wewill illustrate theprocedure firstbyusing the characteristic table and again by using thecharacteristic eq uation.

202 ChapterS Syn chr o nousSequentiallogic

TIle next-stalevalue sof a sequentialcircuirtbat usesJK- or T-ty~flip-f lopscanbederived asfollows:

I. Determine theflip-l1opinputequationsin terms of the presentstateandinput variables.

2. Li..tthebinaryvaluesof eachinputequal ion.

J. Usethecorres pondingflip-flop characteristictableto determinethenext- state values in the slatetable.

As anexample.consider thesequentialcircuitwithtwoJKflip-flopsAandBandoneinput x,as shownin Fig.5.18.Thecircuit hasno outputs;there fore .thestate table doesnot need an outputcolumn.(T heoutputsof theflip-flops mayheconsideredasthe outputs in this case.) The circuitcanbespecified bythenip-flopinputequation s

J_A = B K_A = Bx '

J_B

=

^{x' K}B

=

^{A'x + Ax ' = A$ x}

The state table ofthesequential circui tis shown inTable 5.4.The present-stateandinput columnslist the eight binarycombinations.Thebinaryvalues listedunderthecolumnslabeled flip -flopinput sare norpart of the slatetable,but theyareneed ed for thepurpo-.eof evaluating

the ne xt slateas specified instep 2 ofthe proc edure.These binary:value s are obtain ed di- rect lyfrom the four input equations ina manner similar10 that for obtai ning a U11th table from aBoolean expression.ThenextslateofeachIlip-flop is evaluated from the correspon- dingJandKinputsandthecharac teristictable ofthe JKllip-l1op listed inTable 5.1.There arefourcasesto conside r,When J = I and K = O.the next state is I.WhenJ = 0 and

,

J C/4

J

^K

J

•

Clk

K

.~

B

Clock FIGURE5.18

. S~uentlalcircuitwithJKflip-flop

Section 5.5 Analysisof Clocked Seque ntial Circuits 203

Table S.4

State Table for Sequential Circuit with JK Fllp.Flops

Presen t Next Flip-Flop

State Inpu t Stat e Inputs

A

•

^{x A B t, K, /, K,}

0 0 0 0 1 0 0 1 0

0 0 1 0 0 0 0 0 1

0 1 0 1 1 1 1 1 0

0 1 1 1 0 1 0 0 1

1 0 0 1 1 0 0 1 1

1 0 1 1 0 0 0 0 0

1 1 0 0 0 1 1 1 1

1 1 1 1 1 1 0 0 0

K = I. the next slateis O.When1 = K = O. there isno change of state and the next- slate value is the same asthat of thepresentstate. When1 = K = I,the next-statebitisthe com- plementof thepresent-state bit.Examples ofthe lasttwo cases occur in thetablewhenthe prese ntstateABis10 andinput.risO.lA andKAarebothequalto0 and thepresent state of A is I.Therefore,thenext stateofA remains thesameand is equal 10 1.In the samerowof the table,lBandKBare both equal10I.Since thepresent state ofBisO.thenextstate ofB iscomplemen tedandchangesto I.

The next-state valuescanalsobeobtained byevaluating thestate equationsfromthe char- acteristiceq uation.This isdone byusingthe following procedure :

I. Determinetheflip-flopinput equations in terms ofthepresentstate and input variables.

2. Substitutetheinput equationsintotheflip-flop characteristicequation10obtain thestate equat ions.

3. Usethe correspondingstateequations todetermine the next-state valuesintheslate table.

Theinput equations for the twolKflip-flopsof Fig.5.18werelistedacoupleof paragraphs ago.The charact eristicequations forthe flip-flops are obtained bysubstitutingAorBforthe nameof theflip-flop. insteadofQ:

A(t

+

I) = lA'

+

K'A B(I

+

1) = JB'

+

K'B

Substituting the values oflAandKA frum the inputequations. weobtainthestateequationforA: A(t

+

I) = BA'

+

(Bx' )'A = A'B

+

AB'

+

Ax

The state equation providesthebit valuesfor thecolumn headed "NextStale"forAinthe state table . Similarly.the stareequationforflip-flopBcan be derived fromthe characteristic equa- tionbysubstitutingthe valuesofJeandK_{B :}

B(t

+

I) = x'B'

+

(AEIlx)'B = B'x '

+

ABx

+

A'B x '

204 Chapter5 Synchrono us Sequential Log ic

so i;ii

o

fiGURE 5.19

State diagramof thecircuitof Fig.5.18

o

o

11 S3

o

10 S2

Thestateequation providesthebitvaluesforthecolumn headed"Next State" forBin the state table.NotethatthecolumnsinTable 5.4headed"Flip-FlopInputs"arenotneeded .... hen state equatio ns areused.

Thestatediagramof the seq uentialcircuitisshow nin Fig.5.19.Notethatsincethe circuit hasnooutputs,the directedlinesout of the circlesare marked withone binarynumberonly.

to designa tethe valueofinput.r.

Analysis With T Flip-Flops

The analysisofasequential circuitwithTflip-napsfollowsthesameprocedureoutli ned for JKnip-flops.Thenext-statevaluesinthestatetable canbeobtainedby using eitherthe char- acteristic tablelisted in Table5.1 or thecharacteri sticequation

Q r, +

^I) ~ TEIlQ = T'Q

+

TQ'

Now consider the sequentialcircuitshownin Fig.5.20.Ithastwonip-flopsAandB.oneinput .r,and oneoutputyand can be described algebraicallybytwo inputequatio ns and an output equation:

TA :::: Bx To :::: x

r> A8

The state tableforthecircuit islistedinTable 5.5.Thevaluesforyare obtained from the out- putequation.Thevaluesforthe nextstatecanbederivedfrom the state equationsby substi- tutingT_AandT_Binthe characteristic equations. yielding

A(t

+

I) :::: (B.t)'A

+

(Bx)A' :::: AB'

+

Ax '

+

A'Bx B( ,

+

I) = xEllB

Section5.5 Analysis of Clocked Sequential Circuits 205

o o

o

y

}-- ---;- - --{l O/O } -- --'--- - «Oll!!

J

^{) T A}

I

elk R

I

A

H

T B

OOI!!

CIk 1

R

T

H

Ill!

V Clock reset

(a) Circuitdiagram FIGURE5.20

Sequentialcircuit with Tflip-f1ops

(b) State diagram

Thenext-statevaluesforAandBin thestate tableare obtained from theexpressionsof thetwo stateequa tions.

The state diagram of the circuit is shown inFig. 5.20(b). Aslongas inputxisequal10I, the circuitbehavesas a binarycounter with a sequenceof states 00,01, 10,II ,andback to 00.

Tabl e 5.5

State Table forSequen tial Circuit with TFlip-Flops

Present Next

State Input State Output

A B x ^A B Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0 I 0 0

I 0 I I I 0

I I 0 I I I

I I I 0 0 I

206 ChapterS SynchronousSequential Logic

When .r ;: O.the circuitremains inthesame state.Outputyis equal 10 I when the present stateisII.Here.the outputdepends on the present Mate onlyand isindependent of the input.

Thetwo valuesinside eac hcircleandseparated by a ..lashare for the presentstateandoutput.

Mea ly and Moore Models of Finite State Machines

Themost general model of a sequentialcircuit hasinputs.outputs.and intemalstates.Itis cus- te rnary¹⁰ distin guish between^{(W O}models of seque ntialcircuits:the Meal y modelandthe Moore model. Both areshowninFigure5.21.They differ onlyin!hewaytheoutput is gener- ated.IntheMeal y model.the outputisafunction ef both the presentstareandthe input.In the Moore model. theoutputi", afunctionofonly the presentsta te.Acircuit may havebotht)pe' ofoutputs.The twomodels of a sequentialcircuit arecommon lyreferred10as. afinite statema- chi ne.abbreviatedFS~t.TheMealy modelofa seq uentialcircuit is referred 10 as aMealy FSMorMealy machine.TheMou re modelisreferred10 as aMoore FSMorMoore machine.

Anexamp leof aMealymodel isgiveninFig,5.15.Output)'isa function of both inputr and thepresentslate ofAand8.Thecorres pond ingstatediagram in Fig.5.16sho ws boththe input andoutputvalues. separated byaslashalong thedirected lines betweenthestates.

AnexampleofaMoo remodelis given in Fig.5.18.Here.the outputisafunctionof the pres- entstate only,The correspondingstatediagram in Fig.5.19 has onlyinputsmarked along the

L

•

^{p~ p m}

,Vr s;tS Iatc'

..,

Output

U?mbi ~ ~ -

HfKif,frF

s_

Cumbitl'lli"rnrl

I-

-

[~-";i:~ _A Lotti.

Clod.

I

(.)

Jluof'<',UQdl/lI~

•

,

_J\'ul SIUII' Ollll'ltl

Comhilf(l l imw l

-

^St"t.. Combi""f;rl/l a/

t--

-

^{Logic RegiIfa Lo gic}

Clock

I

OUlp ll U (Moo rN:OfHl

(b '

fiGURE 5.21

Blockdiag ram sofMealyand Moore state mach ine s

Section 5.6 Synt hesizableHDl Models of Sequen tialCircuits 207

directed lines.The outputsarethe flip-flopstatesmarkedinsidethe circles.Anotherexample ofaMoore model isthe sequentialcircuitof Fig. 5.20. The output depends onlyonflip-flop values,andthatmakes it afunction of the presentstateonly. Theinputvalueinthe statedia- gramislabeled alongthe directed line, butthe output value is indicatedinside the circletogether withthepresentslate.

InaMoore model.theoutputsofthe sequentialcircuitaresynchronizedwiththeclock, be- causethey dependonlyon fl ip-flop outputs that aresynchronized withtheclock .InaMealy model,theoutputs may change ifthe inputschange during the clockcycle.Moreover, theout- putsmay havemomentaryfalsevalues becauseofthe delay encounteredfrom thetimethatthe inputs changeandthe timethat the flip-flop outputschange.Inorderto synchronizeaMealy- type circuit,the inputsof thesequentialcircuitmust be synchronized withthe clock and the outputsmuslbesampledimmediatelybeforetheclock edge. The inputsare changedar thein- activeedge ofthe clockto ensure thattheinputs totheflip-flops stabilizebeforethe activeedge of theclockoccurs.Thus, theoutputof theMealymachineisthevaluethatispresent imme- diatelybefore the activeedge of theclock.

5 . 6 SYNTHESIZABLE HDL MODELS OF SEQUENTIAL CIRCUITS

The Veriloghardware descriptionlanguage lHDL) was introducedin Section 3.10.Combina- tionalcircuits were described in Section 4.12,andbehavioralmode lingwithVerilog wasin- troduced in that section as well. Beh avioral models are abstract representations of the functionalityof digitalhardware.Designerswrite behavioral modelstoquicklydescribehow a circuitisto operate, withouthaving10first specify itshardware.Inthis section,we continue the discussion of behavioral modeling and presentdescription andexamplesof flip-flops and sequentialcircuitsin preparationformodelingmore complexcircuits.

Behavioral Modeling

There areIWo kindsof abstract behaviors in the Verilog HDL.Behaviordeclared by thekey- wordinitialis calledsingle-passbehaviorandspecifiesa singlestatementor ablock statement (i.e.. a list of statementsenclosedby either abegin ... endor afork .. .joinkeywordpair ).

Asingle-passbehaviorexpiresafterthe associatedstatementexecutes .Inpractice, designers use single-passbehaviorprimarily10prescribe stimulussignals inatestbench-nevertomodel the behaviorof a circuit-becausesynthesistoolsdonot acceptdescriptionsthatusetheinitial statement.Thealwayskeyworddeclares a cyclic behavior.Bothtypes of behaviorsbeginex- ecuting....-henthesimulatorlaunchesattime1;;:O.Theinitialbehaviorexpiresafterits state- mentexecutes; thealwa ysbehavior executes and reexecutesindefinitely,untilthesimulation is stopped.Amodulemaycontainanarbitrary number ofinitialoralways behavioralstate- ments. They executeconcurre ntlywith respecttoeach otherstartingurtime0 and mayinter- actthro ugh commonvariables.Here 's a worddescriptionof howan always statementworks for a simplemodel of aD fli p-flop:Whenevertherisingedgeof theclock occurs.ifthe reset input is asserted. theoutputqgels0; otherwisethe outputQgetsthe valueoftheinput D. The executionof statementstriggere dby the clockisrepeateduntilthe simulationends.We'll see shortlyhow 10 writethis descriptioninVerilog.

208 Chapter 5 Syn chr on ous Sequential Logic

Aninitialbehavioralstatementexecutesonlyonce.II beginsits executionatthestartof sim- ulation andexpires after allofitsstatementshave completedexecution.Asmentionedatthe endof Section4.12,theinitialstatement isusefulforgeneratinginputsignalsto simulatea de- sign.In simulatingasequential circuit,itisnecessary to generatea clocksourcefortriggering the flip-flops. The follow ingaretwo possibleways toprovideafree-runningclockthat oper- atesfor a specifiednumberofcycles :

Initial begin

clock =l'bO;

end Initia l

begin clock=1'bO;

repeat(3D)

#10clock =-ctccs:

end Initial300 $finls h;

always#10clock=-clock;

Inthe firstversion,theinitialblockcontains twostatements enclosedwithin thebeginandend keywords.The firststatementsetsdock to0attime = O.The second statementspecifiesa loop thatreexecutes30 timesto wait10timeunitsandthencomplemem thevalue ofclock.This pro- duces 15clock cycles,each with acycle timeof20lime units.Inthesecondversion.thefirstinit- lalbehavior hasasinglestatement thatsetsclodto 0 attime = 0,and it thenexpires(causes nofurther simulationactivity).Thesecondsingle-passbehaviordeclaresa stopwatchforthesim- ulation.Thesystem taskfinish causes the simulation to terminate unconditionallyafter300 timeunitshave elapsed.Becausethisbehaviorhas onlyonestatementassociated withit,there isnoneedto writethe begin .. . endkeywordpair. After 10 time units,thealways stateme nt repeatedly complementsdock,providing aclock generator having a cycletimeof :!Olime units.

Thethree behavioralstatementsinthe second example canbewritten inan)'order.

Hereis another waytodescribe a free-runningclock: initial begin clock=0;forever#10 clock=-ciock;end

This version. with lWOstatements on oneline.initializesthe clock and then execute s an in- definite loop(forever)in whichtheclockis complementedafteradelay of 10 time steps. Note thaithesingle-passbehaviorneverfinishesexecutingandsodoesnOIexpire.Another behav- iorwould havetoterminatethesimulation.

The activity associated witheither type ofbehavioralstatement can becontrolled bya delay operator thaiwaitsfor acertaintimeor byan eventcontroloperatorthatwaitsforcertain con- ditionstobecometrue or forspecifiedevenrs (changes insignals)10 occur.Time delaysspec- ifiedwiththe#delay control operatorare commonlyusedinsingle-passbehaviors.The delay controloperator suspends executionofstatementsuntilaspecified timehaselapsed.We'veal- readyseenexamp lesofitsuse to specify signalsinatest bench.Anotheroperator.@.is called the event control opera lOrandisused10 suspendactivityuntilan event occurs.Aneventcan beanunconditionalchangeinasignalvalue(e.g.•@A)oraspecifiedtransitionofa signal value (e.g.•@ (posed geclock» ,The generalformofthistypeofstatementis

always@(event controlexpresston)begin

/IProce dural assi gnmentsta teme nts that executewhen the condition ismet end

Section S.6 SynthesizableHDL Modelsof Sequential Circuits 209

Theevent controlexpressionspecifies theconditio nthaimustoccurtolaunch executio nofthe procedura lassignmentstateme nts. The variablesin the left-hand sideofthe proceduralstate- ments mustbeoftheregdata typeand mustbe declared as such.The right-hand sidecanbe anyexpress ion that produces a valueusing Verilog-defined opera tors.

The eventcontrolexpress ion(alsocalled the sensitivitylist) specifies theevents that must occur[0initiateexecution of the proceduralstateme ntsassociatedwiththealwaysblock.State- ments withi nthe blockexecutesequentially from toptobottom.After the laststateme ntexe- cutes.the behavio r waits fortheeventcontrolexpression tobe satisfied. Then the state ments are executedagain. The sensitivity list canspecifylevel-sensitiveevents,edge-sensitiveevents, or a combinationofthe two.Inpractice,designers do not makeuse ofthe thirdoption.because this third formis notonethatsynthesis tool sare able to translate into physical hardware. Level- sensitiveeventsoccurin combinationa lcirc uitsand inlatches.Forexample, the stateme nt

always@(AorBor C)

willinitiateexecutionof the procedural stateme ntsin theassociatedalways block ifachange occursinA,B,or C.In synchrono ussequent ialcircuits,changes inflip-flops occuro