SectionS.8 Design Procedure 229
,
~
~J , 0
IS
l£4Z I
J )§
I
I
Ciock
T
A
8
B'
)
FIGURE5.29
logic diagr am ofseq uence detector
230 Chapte r5 Synch ronous Sequential Logle
Table 5.12
Flip-flopExcitationTobles
Q( t ) Q(l
=
1)J «
Q(l) Q(t=
1)~
0 0 0 X 0 0 0
0 I I X 0 I I
I 0 X I I 0 I
I I X 0 I I 0
(a )JK (b)T
how therequiredtransitionis achieved. There arefourpossibletransition sfrom the presentslate tothenextstare .Therequiredinputconditionsforeachofthe four transitionsarederivedfrom the informationavailable inthecharacteristictable.The symbolX in the tables represents a don'H arecondition, which meansthatitdoes not matterwhethertheinputis 1or O.
The excitationtablefor theJK flip-tlop isshownin part (a).Whenbothpresent"lateandnext state areO.theJinput mustremainat0andtheKinput canbeeither0or I.Similarly...henboth presentstateand next state arc 1.theKinputmust remain at O.whiletheJinputcanbe0 or 1.
Iftheflip-flop istohaveatransitionfromthe O-statetothe l-state,Jmustbeequalto I.since theJinputsetsthe flip-flop.However.inputKmaybeeither0orI.IfK
=
O. the J=
Icon- ditionsets the flip-flopas req uired;ifK = Iand J = I.theflip-flop iscom plemented and goesfrom theOcstatctothe I-state asrequired.Therefore.the Kinputismarkedwith a don't- careconditionfor theO-to-Itransition.Foratransitionfromthe I-stateto the O-state. wemust haveK = I. since theK inputclears the llip-flop.However.theJ input maybeeither a or 1.sinceJ
= a
hasno effectandJ=
1 together withK=
1complementstheflip-flopwith a re- sultant transitionfromthe l-statetothea-state .The excitat iontable fortheTflip-Ilop is shown inpart(b).Fromthecharacteri...tic table.we findthatwheninputT = I.the stateoftheflip-flop iscomplemented. and whenT = O.the stateof the flip-flop remainsunchanged.Therefore.whenthe state of the flip-flopmustre- main thesame.the requireme nt isthatT = O.Whenthestateof theflip-flopha..to becom- plemented.Tmust equal I.
Synthesis Using JK Flip-F lops
ThemanualsynthesisprocedureforsequentialcircuitswithJKflip-flopsisthe same aswith Dflip-flops.exceptthat the inputequationsmustbeevaluatedfrom the present-statetothe next- state transition derivedfromtheexcitationtable.To illustratetheprocedure.we willsynthe- size thesequentialcircuitspecifiedbyTable 5.13.Inadditiontohaving columnsforthepresent state,input.and nextstate.asinaconventionalstatetable.the tableshowsthe nip-flopinput conditionsfromwhich theinput equationsare deri ved.Theflip-flopinputs are derived from thestate tableinconjunctionwith the excitationtablefortheJKflip-nap.Forexample.in the firstrow ofTable 5.13.wehave a transitionfor llip-flop A from 0 inthe present stateto 0 in the nextstate .In Table 5.12.fortheJKflip-flop.we find that atransition ofstates frompres- entstate atonextstate0 requiresthatinputJbe0andinputKbe a don't-care.So0andX are
Section S.B Design Proced ure 231
Table 5.1J
Srat~TabkandJK flip-FlopInputs
Present Nellt
State Input State Fllp.FlopInputs
A
• •
A•
J•'.
J.'.
0 0 0 0 0 0 X 0 X
0 0 I 0 I 0 X I X
0 I 0 I 0 I X X I
0 I I 0 I 0 X X 0
I 0 0 I 0 X 0 0 X
I 0 I I I X 0 I X
I I 0 I I X 0 X 0
I I I 0 0 X I X I
enteredin the firstrow underJ,4andKA,respectively.Sincethefirstrowalsoshows a transi- tion forflip-flopBfrom0 inthepresent stateto 0in thenext state, 0 and X arcinserted into thefirstrowunderInand KB,respectively,The second row ofthetableshowsatransition for flip-flopBfrom0 in the presentstateto Iinthenextslate. From the excitat ion table. wefind thatatransition from0to IrequiresthatJbeIandKbea don't -care.so Iand Xarecopied into the second rowunderJIlandKn.respecti vely.The proce....iscontinued foreachrow in thetable and for each nip-flop.with theinputcondi tionsfromthe excitationtablecopied into theproper rowoftheparticular flip-flop being considered.
Thenip-flop inputsinTable 5.13 specifythe truth tableforthe input equationsasa func- tion of present stateA,present stateB.and input.r.The inputequationsare simplified inthe maps ofFig.5.30.The next -starevaluesare nOI used duringthesimplification,sincetheinput equation sare a function ofthc presentstate andtheinputonly.Notethe advantageof usingJ K- type nip-flops whensequential circu itsare designedmanually.Thefactthat there aresoman)' don 's-careentriesindicatesthat the combinationalcircuit for theinputequationsislikelytobe simpler,becausedon' t-carenunrermsusuallyhelp inobtaining simplerexpressions.Ifthereare unused statesinthestate table. there willbeadditionaldon't-care conditionsin the map.
The fourinput equationsforthepairofJKflip-flopsarclisted underthemapsofFig.5.30 . The logicdiagram (schematic)of the sequentialcircuitisdrawnin Fig.5.3 1.
Synthesis Using T Flip-Flops
Theprocedure for synthesizingcircuits usingTflip, flopswillbedem onstrated b),designin g abinary counter.An n-bitbinarycount er consistsof n flip-flops thatcancount inbinary from 0102" - I.Thestalediagramofathree-bit counterisshownin Fig .5.32.As seenfrom
e e
binary statesindicated in..idethecircles.the nip-flopOUIPUISrepeat the binarycountsequence witha returnto 000 after 111.Thedirected linesbetweencircles arenotmarked with input andoutput valuesas in otherstatediagram s.Rememberthatstate transitions inclocked se- quentialcircunsoccurduring a clock edge;the flip-flop..remainintheir present slate sif no clockisapplied.Forthat reason.the clock does nOIappear explici tly a!'>an input variablein
232 Chapte r S Synchronou sSequentia l lo gic
B B
B,
A
..
00-,
0'' .
II.,
100 X X X X
I ,
".. .. , ..
, A
B, ,
A 0
..
~, "01..
II 17
10'j'"
I , - ,
X..
X..
X..
I ~
,
A
,
I"- Bx'
B B
B"
A 00 OJ II 10
"
-, II"',•
u
X XI I '
I ,
" XI l: , -. , " ..
, A
B"
A
..
~II r
0t
''
-.II«..
100 X X
A
I ,
m,I
"' ~ I
"~ ..
XFIGURE5.30
MapsforJandKinputequations
, J '
v
J
JCIt
J ~ ; ,
J
CIk
11 .9 ,
A
A'
B
B'
Clod FI(j,URE5.:31
Logic diagram for sequenti al circuit withJI(flip-flops
Sectio nS.8 Design Procedu re 233
WI III
0 '.
@l e---' e
FIGURE 5.32
State diagramof three-bit binarycounter
aslate diagram orslate table. From thispoint of view.thestate diagram of a counter doesnot havetoshow inputandoutput valuesalong the directedlines.The only input to the circuitis the clock.and the outputs arespecified bythepresentstate oftheFlip-fl ops. Thenext stateof a counterdependsentirelyon itspresent state,and thestatetransitionoccursevery time the clock goesthrough atransition.
Table5.14isthestatetableforthethree-bit binary counter.The three flip-flopsaresym- bolized byA2•A].andAo.Binary counters are constructed mostefficiently withTflip-flops because oftheir complement property.The flip-flopexcitation fortheTinputsisderivedfrom theexcitation table oftheTnip-flop and by inspection of thestate transition of thepresentstate tothe next state.As anillustration.consider the flip-flopinputentries forrow 001.The pres- entstate hereis 001andthe next stateis010.which isthenext countin thesequence. Com- paringthesetwo counts,wenotethatA2goes from 0 to O. soTA2ismarkedwith 0 because flip-napA2must not changewhenaclock occurs. Also,AI goesfrom 010I, soTAJismarked witha I becausethisnip-flop must becomplemented in the nextclock edge.Similarly,Ao goesfrom Ito 0,indicatingthaiit mustbecomplemented.soTAOismarkedwitha I.The last row. with present state II I.is compared with thefirstcount000,which isitsnext state. Going from all tsto allO'srequiresthat allthreeflip-napsbecomplemented.
Table5.14
5tate Table for Three-BitCounter
Present State Next State Flip-FlopInputs
A, AI A, A, A,
AoT " T Al T"
0 0 0 0 0 I 0 0
0 0 I 0 I 0 0 I
0 I 0 0 1 I 0 0
0 I I I 0 0 I I
I 0 0 I 0 I 0 0
I 0 I I I 0 0 I
I I 0 I I I 0 V
I 1 1 0 0 0 I I
234 Chapter5 Synchronous Sequential Logic
~I
11 10
01
A1Au A
. ,
,
00 011 1
10" .
.',I'~ J~f:
m,0 . ,;1//
,1 1 .
, m, ~A"~}~ ;~,
"'.
A
A
FIGURE 5.33
Mapsfor three-bit binarycounter
A,
FIGURE 5.34
logic diagramof three-bit binarycounter
Theflip-flopinputequationsaresimplifiedinthe maps ofFig.5.33.Note thaiTAOhas t's in all eight mintermsbecausethe leastsignificant bit ofthecounteris complementedwith each count.A Booleanfunctionthatincludesallmlntermsdefinesa constantvalue of J.The input equationslisted under each mapspeci fy the combinational part ofthecounter.in- cludingthesefunct ions with thethreeflip-flops,weobtain the logic diagramofthecount- er.as shownin Fig. 5.34.Forsimplicity,the resetsignalisnot shown, butbeawarethat every design sho uldinclude aresetsignal.