Structural Description of Clocked Sequential Circuits

Combinationallogic circuitscanbedescribedin Verilogbyaconnectionofgates (primiti ves and UDPs). by dataflow statements(continuousas..ignmems). orbylevel-sen sitive cyclic be- haviors (alw ays blocks),Sequential circuits arecomposed ofcombinational logic and flip- flops,andtheir HDLmodelsusesequentialUDPsand behavioralstatement..(edge-sensitiv e cyclicbehaviors)10describethe oper ationof flip-flops.Oneway10describeasequentia lcir- cuitusesacombination ofdataflow and behavioralstatements.The flip-flop s are described withan alwaysstatement.The combinat ionalpart can bedescribed withassig n stateme nts and Boolean equations,Theseparatemodulescanbeco mbinedtofonnastructuralmodelby instantiationwithinamodule.

The structu raldescriptionofaseq uential circuitisshownin HDL Example5.7.Wewant to encouragethe readerto consideralternative ways to modela circuit. soas a point of com pariso n. we first presentMoore_MudeCFig_5_20.a Verilogbehavioraldescriptionof the machine hav ing the stale diagram show n inFig.5,20,Thi.. style ofmodeling isdirect.

218 ChapterS Syn ch ronou sSequential Logle

An alternative style. used inMoore_ModeCSTR_Fig_5_20. is torepresent the struc tu re shown inFig.5.20<a).This sty leusestwomodu les.The firstdescribesthe circuit ofFig.5.20l a).

Thesecond describestheTflip-nopthat willbeusedbythecircui t.Wealso sho wtwoways to modelthe Tflip-flop.The firstassertstha r. areveryclock rick. the valueofthe ourput ofthe flip·flop toggles ifthetoggle inp ut is asserted.Theseco nd model describesthe be- havior ofthe toggle ffip-Ilop intenusofits characteristic equation.The tim style is at- tractive because itdoes not require the reader to remember the characte rist ic equatio n.

Nonetheless.themodels are interchangea bleand willsynthesize tothesamehardware cir- cui t.Atest benchmoduleprovidesastimulusfor verifying the functionalit y ofthecircuit.

The sequent ialcircuit is a two-bit binary countercontrolled by inputx_ill. The output, y_out,is enabled whenthecountreachesbinary II.Flip-flopsAand8areincluded as out- putsinordertochec ktheiroperation . Theflip-flopinput equationsandtheoutputequation are evaluate d with continuous assig nment(a ssip;n) sta tements having the correspond ing Boolean express ions.Theinstantiated Tflip-flops usc TA and TBasdefinedby the inpu t equations .

The second moduledescribesthe Tflip-flop.Theresetinputresetstheflip-fl op to0 with an active-low sig nal. Theoperationof theflip-nap is..pccifiedbyitscharacter istic equation.

Q(I

+

I) - QIIiT.

The testbenchincludesbothmodelsofthemachine.The stimulusmoduleprovide.. com- mon inputs tothecircuitsto simultaneouslydisplay their OUtput responses.The first in itia l blockprovid eseight clockcycle..withaperiodof IOns.The secondinitia lbloc k specifies a togglingofinputx_illthatoccurs atthenegative edgetransitionof theclock .The resultof the simulationis shown inFig. 5.24.Thepair(A.B)goesthroughthebinary sequence00.01. 10.

II,and back 1000.The change inthecountistriggeredbyapositive edge of the clock. pro- videdthatx_ill :: I.Ifxjll :: O.thecountdoesnotchange.y_oll1is equal to I when bothA and Bare equalto I.Thisverifiesthemain functionalityofthecircuit. butnot areco veryfrom anunex pectedreset event.

HIlI.Example5.7

/IState-diagram-basedmodel(V2001,2005) moduleMoore_ModelJig_5_20(

output Lout,

Input x_in.clock, reset ):

reg[1:OJ state;

parameter 80= 2'bOO.81=2'b01. 82=2·b10.83=2'b11; always@(posedgeclock.negedgeresell

If(reset==0)state<=80; IIInitializeto state80 else case(state)

80: jf(x_in)stale<= 81;elsastale<=80;

81: If(x_in) state<=82;elsestate<=81;

Section S.6 Syntheslzable HDl Models of Sequential Circuits 219 52: if(xJn)state<=S3:elsestale<=52:

53: if(x_in) slate<=SO;elsestate<=53;

endcase

assignLout=(stale ==53);

endmodule Ifstructuralmodel

moduleMoore_Model_5TRJ iIL5_20(

output LOUt,A,B.

Input x_in.dock.reset ):

wIre TA,TB;

IIOlJlpUtofflip-flops

IIFlip-flopinputequations assignTA= xJ n&B:

assignTB = xJn:

1/Output equation assignLout =A&B;

1/InstantiateToggle flip-Ilops

Toggle_llip-'loP_3M_A(A.TA.clock.resell:

Toggle)lip-"op_3 M_B(B.

re .

^{clock.reset):}

endmodule

moduleToggle_lIip)lop(0.T.ClK,R5T_bl;

output Q:

Input T,ClK.R5T_b:

reg 0:

always@(posedgeCLK.negedgeRST_b) if(RST_b==0)

a

^<=1bO:

elseif(T)

a

^<=

-o :

endmodule

/IAlternativemodelusing Characteristic equation 1/ module Toggle_flip_flop(Q,T,CLK.RST_b):

1/ output Q:

If input T,CLK,RST_b;

1/reg 0;

If always@(posedgeCLK,negedgeRST) If If(RST_b==0)

a

^<=1'bO;

1/ else Q<=QAT;

If endmodule

220 Chapter5 Syn chronousSequential logic

moduletMoore_Fig_5_20;

wire 1""y_out_2,1....Y_out_l;

reg tx-,n,tclock. Ueset;

Moore_Model]i9-5_20 Moore_Modet STR_Fig_5_20

M1(1""y_OUU ,I_x_in,U:tock.tJeset);

M2(t y_out_2.A.B,'-)!,_in,U::lock.Uesel):

Initial#200^Sfinish;

initi albegin Ueset=0;

U:lock=0;

#5 Ueset=1;

repeat(16)

#5t_clock=~U:lock;

",

init ialbegin t_xjn=0;

#151_x_in=1; repeat(8)

#10t x

- -

in=~t

-

x

-

in'^'

en'

endmodule

" .

o '00

v

, ~.

,

'_cloclt.

~

'-rtH I --'

I~j..

I..)'~<II"-' (->,_olll..1

A 8

FIGURE 5.24

Simulation outputofHDlExample5.7

Sedion5.7 State Reduct io nand Assignment 221