234 Chapter5 Synchronous Sequential Logic
~I
11 10
01
A1Au A
. ,
,
00 011 1
10" .
.',I'~ J~f:
m,0 . ,;1//
,1 1 .
, m, ~A"~}~ ;~,
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A
A
FIGURE 5.33
Mapsfor three-bit binarycounter
A,
FIGURE 5.34
logic diagramof three-bit binarycounter
Theflip-flopinputequationsaresimplifiedinthe maps ofFig.5.33.Note thaiTAOhas t's in all eight mintermsbecausethe leastsignificant bit ofthecounteris complementedwith each count.A Booleanfunctionthatincludesallmlntermsdefinesa constantvalue of J.The input equationslisted under each mapspeci fy the combinational part ofthecounter.in- cludingthesefunct ions with thethreeflip-flops,weobtain the logic diagramofthecount- er.as shownin Fig. 5.34.Forsimplicity,the resetsignalisnot shown, butbeawarethat every design sho uldinclude aresetsignal.
Problems 235
correct.Ifsynthesistools and an ASICcell libraryare available. theVerilog descri ptions developedfor Prob\ems 5.34-5.46canbe assigned as ">)'l'Ithesis exercises.The gate-\e\'e\ circuit prod uced b)'the
synthesis tools should besimulated and compared with the simulatio n results for the presynthesis model.
5.1 The Dlatch ofFig.5.6is constructed withfourNANDgates and aninverter.Consider thefol- lowing threeother ways for obtai ningaDlatch.and ineachcasedrawthe logic diagra m and verify the circuitoperation;
(a) UseNORgatesfor theSRlatch part and ANDgatesfor the othertwo. An invertermaybe needed .
(b) Use NORgatesfor allfourgates.Invertersmaybeneeded.
(c) Usc four NAND gatesonly (withoutaninverter).This canbedonebyconnect ingthe output oftheupper gate in Fig.5.6(the gatethat goesto theSRlatch)to theinputofthelowergate (instead of theinverter output).
5.2 Con structaJKflip-flop. using aD flip-flop . a two-to-one-line multiplexer. andan inverter.
(HDL-seeProblem 5.34.)
s .J
Showthat the characteristicequation forthecomplement outputofaJKflip-flop is Q' ( I+
I)= J'Q' + KQ5.4 APNflip-flophas four operations.clear10O.no change.complement.andsetto I.wheninputs PandNare 00.01.10.and II. respectively.
(a) Tabulate the characteristic table. (h)·Derive thecharacteris ticequation.
(c) Tabulatethe excitationtable. (d ) ShowhowthePNflip-flop canbeconverted to aDflip-flop.
5.5 Explainthe differencesamonga truthtable.a state table.acharacteristictable. andanexcitation table.Also.explainthedifferenceamongaBoolean equation.a stateequation. a characteristic equation. and aflip-flop inputequation.
5.6 Asequentialcircuit with twoDflip-flopsAandB.two inputsxandy, andoneoutputzis speci- fied by the followin g next-state and outputequations(HDL-seeProblem 5.35);
A(t + I) = x'y +xB B(t + I) = x/A + ,.
,
- A (a) Draw thelogic diagramofthecircuit.(b) Listthestaletableforthe sequentialcircuit.
(c) Draw thecorrespo nd ingstate diagram.
5.7· A sequentialcircuit has oneflip-flopQ.two inputsxandy,and oneoutputS.Itconsists of a full- addercircuitconnectedtoaDflip-flop.as shown in Fig.P5.7.Derivethestaletable andstate diagramof thesequentialcircuit.
5.S· Derive thestatetable and the statediagramof the sequentialcircuitshownin Fig.P5.8. Explain the functionthat the circuitperforms.(HOt-seeProblem 5.36.)
236 Cha pterS Synchronous SequentialLogic
Clar/c
, ~[[--s c
,
Q
FIGURl P5.7
1
8']A'
A 8c~
~ $j
T_~"§J, C~ TI I
~ YT ~
FIGURE PS.8
5.9 Asequential ctrcvitha.\IVioJKflip-flopsAand8andoneinputx_The
cecuu
Isdescribedb) lhefollow ing flip-flop inpul equatjon c
JA"" x KA-B'
JB- x K. - A
(a)· Derivethe~taleequat ionsA(t + I)and8(t + I)by !\Ub:.litutingtheinpul equations furthe
JandKvari ables,
(b) Draw thestale diagramof thecircun.
5.10 Aseq uentialcircuith~IwoJKfiip-flops A and 8.lwoinpul>.J: andy.andoneoutput:.Theflip- flop input equationsandcircuiloutpurequationare
JA - Bx + B' ,.'
J. "" A'x
KA-= B'x}-'
KB"" A + X}-'
Problems 237
(a} Drawthelogicdiagramofthecircuit.
(b) Tabulatethestatetable.
(c)~Derivethestate equationsforAandB.
5.11* Startingfrom stale 00 inthe state diagram of Fig. 5.16,determ ine the state transition s and outputsequence that willbe generated whe nan input sequence of 010110 11101 1110 is applied.
5.12* Reduce the number of states in thefollowingstate table,andtabulat e thereducedstate table:
Ne xtStat e Output
Prese nt State X
=
0 X=
1 X=
0 x=
Ia f b 0 0
b d
,
0 0"
f e 0 0d
, ,
I 0,
d c 0 0f f b I I
g g h 0 I
h g u I 0
5.1 3'" Starting fromslate11andtheinputsequence 011100100II.determinetheoutputsequencefor (a) thestate table of thepreviousproblemand
(b) the reducedstatetablefromthepre viousproblem.Showthaithesameoutputsequenceis ob- tained forboth.
5.14 Substitute binary assignment2fromTable 5.9 tothe stalesinTable5.8,and obtainthebinarystate table.
5.15* List a statetablefor theJKflip-flop ,usingQasthe presentand nextstate andJandKasin- puts.De signthe sequential circui t specified bythe statetable,andsho w that itisequivalentto Fig.5.12(a).
5.16* Design a sequentialcircuit withtwoDflip.flopsAandBandone inputx_in.
(a) Whenx_in = 0,the state ofthecircuit remains thesame.Whenx_in= I,thecircuitgoes throughthe statetransitionsfrom00 to 01. toII,to 10,backto 00,and repeats.
(b) Whenx_ill= 0,thestateofthecircuitremainsthesame.When-e.,in = I,the circuitgoes through thestate transitionsfrom 00to II,to01,to10,backto 00,and repeats.(HDL-see Problems 5.38.)
5.17 Design a one-input, one-outputserial2' scomplementer. Thecircuitaccepts astri ngof bitsfrom the input andgeneratestheZ'scomplementatthe output.The circuitcanbereset asynchronously to stan andend theoperation. fHDL-seeProblem 5.39.)
238 ChapterS Synchronous Sequenti al Logle
5.18· Design asequentialcircuitwithtwoJKflip-flopsAandBand twoinputsEandF.1fE ""O.the circui t rcrnainvin thesamestate regardlessofthe value ofF.Whe nE "" 1andF - I.thecir- cuitgoesthro ugh thestatetransitionsfro m00to01.to10.to 11.backto00. andrepeats.When E = IandF = O.the circuitgoesthroughthe statetransitionsfrom00to 11.to 10.to Ol.bac k to 00.andrepeats.(HDL-seeProblem5.40.)
5.19 Asequentialcircuit hasthreeflip-flopsA.B.andC:one input",_in:andoneOUtpu ty_out.The stalediagram is shownin Fig.P5,19.Tbecirc uitis tobedesignedbytreatingmeunusedstates asdon't-care conditions.Analyzethecircuitobtained fro m the design todeterminetheeffect of the unusedstates.(HDL- seeProblem 5.4 1.)
(a)·UseDflip-flopsinthedesign.
(b) UseJKflip-flopsin the desig n,
0,0 001
III 1,0
0,0
FIGUREPS.19
0,0
5.20 Design thesequentialcircuitspecifiedbythe statediagramof Fig.5.19.usingTflip-flops.
5.21 Whatisthemaindifferencebetwee naninitialstatementandana1"-a)1istatement inVerilogHDL?
5.22 Draw thewav eformgene ratedbythe following statements: (a) Initialbegin
w=O; #15w= 1; #6Ow=O; #25w=1; #40w= O;
end (bl initialfork
w=O; #15 w=1; #6Ow=O; #25w=1; #4Ow=O;
join
5.2)- Considerthefollowingstatements. assumingthatRegAcontainsthevalueof30initiall)':
(a) RegA= 75;
RegS=RegA:
(b) RegA <=75;
RegS<=RagA:
What are the valuesofRegAandRegBafterexecution ?
5.24 Write and \c rif )'an HDLbehavioraldescripnon of apositive- ed ge-sensitiveDflip·fl opwith
(a) acnve-jowa~)nchronousp«'K'1 and clear.(Th ist)'peofflip-fl opiS~"lIinFig.11.13.) lb) active-low synduOt\OUsptc'>C\and deat".
S.2S Aspecialposuive-edge-triggered flip- flop hasIWOinplllSDIandD1andacontrol inpullhal cbooees betweentheIWO.
wrue
andvenfyanflD LbehOls'iorallbcrip(ionof thisflip-flop.S.U Write andverifyanilDL bd lol \ioralde!;cription oftheJKflip-Ilop.usinganif-eh estatemen tba!lC\l onthesalue ofthepre-em"'ate.
(a)-Considerthe charac1erislkequation whenQ .. OurQ.. 1
tb) Con side r howtheJandKinpul s affect theoutputof the flip-flo pateachclocklick. 5.27 Rewrite and s'erifythe descriptionofHD LExamp le5.Sby combining theSla{e transition sand
outputintotinealwlllliblock.
5.U Sim ulatethesequentialcin:uitshowninFig. 5.17.
(a) WriteIheHDl tkM'riplio nofthe stalediagram(Le..abehavioralmodel).
(b) WritetheHDLdesc riptionofthecircuitdiagram(i.e.• a structuralmodel).
(c) WriteanIlDl stimuluswiththesequence00.0I. II.10ofinputs.Verifythat theresponse is thesame for hothdescriptions.
5.29
wrne
a behavioralde!>Cri pliunofthestate mach inedescribedby thesla te diagr am shown in Fig.P5.19.wnre
ale~1bench andverifythefunc uonaluyof lhedc:~ription.5.30'" Draw'the logicdiagramforthe"Cq uentialcircuitdescribedbythefollowingHOlmodule:
moduleSeCLCkl(InputA.B.C,ClK,outputregQ);
re gE;
always@(pos edgeCl K);
begin E<=A&B;
Q<= EIC;
end endmodule
What chan ge-,ifan)',lIlU~1beincfuded inIhecircuit ifthe lavttwcstatementsuseblockingin- steadofnunblocki ngas"ig nme nt?
5.31. Ho w~houldlhedcscnpnoninProb lem5.30bewnnenM)Ihal thecircuit hasthesame behavior whenthea,,~ignmenbaremadewith = insteadofwith < ..'!
5.32 Usinganinitialstatementwith,Ihc jtin ... end block.writeaVo:rilogdescriptionofthewave- forms sho wninFig.P5.32.Rc po:alusingafurk ••• joi nblock.
5.33 Explain whyitisimportant thatthevtimulus signalsinateet benchbesynchronizedtotheinec- riveedgeoftheclockofthe seque ntialcircuitthatis10betested,
5.W Using behavioral modelsfflrtheDflip-flo p andthe inverter,writ e and ve rif)'an HDl modelof theJ·Kflip-Ilopdescribed inProble m 5.2.
5.35 Wri te and verityannO Lmodel oftbe sequentialcircuirdescribe din Problem 5.6.
240 Cha pter5 Synchro no us Seq ue ntia l logi c
enable A B C D E F
I
0 1 0 2 0 FIGUREP5.32
Waveforms for Proble m 5.32
I
'0 60
I
70
S.36 writeand verify an HDl structuraldescription of the machine ha vingthecircuit diagra m (schema tic ) showninFig .P5.8.
S.37 Write and verifyHDl behavioraldescriptions of thestatemachines ..hewninFig.5.25and Fig.5.26.write atest bench 10comparethe staresequencesandinput-outputbehaviorsofthe two machines.
5.38 Write andverifyanHDl behavioraldescript ion ofthe machinedescribed in Problem~.1 6.
5.39 Writeand verifya behavioraldescriptionofthe machinespecifiedinProblem5.17.
5.40 Writeandverifyabehavioraldescri ptionofthe mac hine..pecifiedin Problem5.JS.
5.41 Write and verifya behav ioraldescriptionof themachinespecifiedinProblem 5.19.(Him:See thediscus-ionof thedefaultcase itemprecedin gHDlExample~.8inChapter~. I
5.42 Write andver ify anHDl structuraldescriptionof thecircuitsho wn inFig.~i.29.
5.43 Write andverifyanHDl behavioraldescriptionofthethree -bitbinarycountershoy,ninFigure
5.3~.
5.44 writeand verifyaverilo gmod elof aDflip-flophaving synchronou..reset.
5.45 Write and verify anHDl behavioraldescriptionof theseque nce detectordescribedin Figure 5.27