5.7 Super Voltage Converter (Charge Pump)
5.7.4 Basic Negative Voltage Converter
Figure 5-51 shows the ICL7660S connected in the basic negative voltage converter configuration. The output at pin 5 is approximately equal to the input at pin 8, except that the voltage polarity is inverted. A positive supply of+1.5 to +12 V is converted to a negative output of-1.5 to -12 V. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltages below 3.5 V.
The output impedance RQ at pin 5 is a function of the on-resistance of the in
ternal MOS switches (see Fig. 5-50), the switching frequency, the capacitance val
ues of Cj and C2, and the ESR of Cj/C2. From a simplified design standpoint, R0
should be minimum so that the available output is maximum with a given output voltage. R0 decreases with an increase in Cj/C2 capacitance value and switching fre
quency but increases with an increase in ESR.
In theory, the output resistance can be decreased to any value by increasing the switching frequency and the capacitance of Cj/C2. However, there is a practical limit set by the ESR of Cj/C2. (A small increase in ESR will offset large increases in frequency and capacitance values.)
Figure 5-52 shows the effect of oscillator frequency on output resistance, to
gether with many other performance characteristics of the basic negative voltage converter function. The circuit of Figure 3 referred to in Fig. 5-52 is the test circuit shown in Fig. 5-53.
5.7.5 Output Ripple
The ESR of Cj and C2 also affects the ripple voltage at pin 5. As always, a low ESR capacitor produces a lower output ripple.
5.7.6 Paralleling Devices
Any number of ICL7660S converters can be paralleled to reduce output resis
tance. The reservoir capacitor C2 serves all devices, but each device requires a sepa
rate pump capacitor Cr The resultant output resistance will be approximately:
ROUT(ofICL7660S) R OUT
n(number of devices)
1 0 M F = =
T = - V IOMF
Figure 5-51. Basic negative voltage converter configuration (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-111)
Figure 5-52· Negative voltage converter characteristics (Harris Semiconductor, Linear and Telecom ICs, 1991, pp. 2-108-109) TYPICAL PERFORMANCE CHARACTERISTICS OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE -55 -25 0 25 50 100 125 TEMPERATURE(°C)— 0088-5
OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 0088-6
OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE ■OUT=?0"A.V*= <0V -50 -25 0 25 50 ?i 100 125 TEMPCRATUBt(°C) POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSC. FREQUENCY 80
V* -5\ ,ΊΙί TA=25«C Uli ΐ ιίι m
III
il! ill! !!!!!: t"~ '| i i
Τψ ι
Hill || i M ! !, '·· ϋΙΙ' '■' 'I i ; jj—--T'-rji
! \ l
\ ! \HI i l\ 1 llf l
Lt J Li-iH
! i OSC FREQUENCY F0SC(Hz) 0088-8FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSC. CAPACITANCE AS
UNLOADED OSCILLATOR FREQUENCY A FUNCTION OF TEMPERATURE 18 16 14 12 10 8
1 *- • ; -=/
/- V* = 10V
r* =5 v
/ -50 -25 0 25 50 75 100 125 TEMPERATURE(°C)C
I'
CD a. 3I
S a 3- CDFigure 5-52· (continued) TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT 1 ? ° \ " \ -*
l s
V*=5 I V25°C 10 20 30 40 LOAD CURRENT (mA) — 0088-11SUPPLY CURRENT & POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT 100 90 80 70 60 2 50 1 j j- /Λ---4-- — 1 - ] 50 S 40 U4- -J^-U-i-··!- I 40 30 20 10
1
— -r ■ --T'y
— '\"χ7\~
! - ■¥/* ~/\ v*= !TA=
-A-- 1
—-,— l_. . 1. -..-4 -
5V , 25ocr L_. . i,. i 10 20 30 40 50 60 LOAD CURRENT (mA) —OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT LOAD CURRENT (mA) SUPPLY CURRENT & POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAO CURRENT 100 Ï 70 V*=2V V=2*«C
16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0
OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY L0A0 CURRENT (mA)
100 1K 10K 100K OSCILLATOR FREQUENCY (Hz) NOTE 6: These curve« Include In fte supply current lhat current fed directly Into the load RL from V-»- (see Figure 3). Thus approximately half the supply current goes directly to the positive side of the load, and the other half, throught the ICL7660S. to the negative side of the load, ideally, VOUT * 2 V,N. Is>2 lL. so V,N x ls * VOUT x lL.
« - 0 (45V)
NOTE 1: For large values of Cose (> lOOOpF) the values of C, and C2 should be increased to 100pF.
Figure 5-53· Voltage converter test circuit (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-110)
5.7.7 Cascading Devices
Figure 5-54 shows the circuit for cascading devices to increase output voltage.
The ICL7660S can be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, because of the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by:
where N is an integer representing the number of devices cascaded. The resulting output resistance is approximately the weighted sum of the individual ICL7660S R0UT values.
5.7.8 Changing Oscillator Frequency
Because of noise or other considerations, it might be desirable to alter the os
cillator frequency. This can be done by one of several methods described in the fol
lowing paragraphs.
}0μΓ=.
•MOTE 1: VOUT -nV + for 1.5V <; V + ü 12V
Figure 5-54. Circuit for cascading super voltage converters (Harris Semiconductor, Lin
ear and Telecom ICs, 1991, p. 2-112)
Figure 5-55· Circuit for external clocking (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-113)
The oscillator frequency can be increased by about 3.5 times when the boost pin (1) is connected to V+. The result is a decrease in output impedance and ripple.
This is of major importance for the surface-mount applications where capacitor size and cost are critical. With the increased frequency, smaller capacitors (such as 0.1 pF) can be used to get output currents comparable to those when the IC is operated at the free-running frequency of about 10 kHz and with Cj/C2 at 10 or 100 μΡ. This is shown in Fig. 5-52 (output source resistance as a function of oscillator fre
quency).
The oscillator frequency can also be increased by overdriving from an exter
nal clock as shown in Fig. 5-55. To prevent latchup, use a 100-kQ resistance in se
ries with the clock. If the clock source is TTL, rather than the CMOS shown, connect a 10-kQ pull-up resistor to the V+ supply. Note that the pump frequency is one-half the clock or free-running oscillator frequency. Output transitions occur on the positive-going edge of the clock.
It is also possible to increase the conversion efficiency of the ICL7660S (at low load levels) by lowering the oscillator frequency. This is shown in Fig. 5-52 (power conversion efficiency as a function of oscillator frequency). The oscillator frequency can be lowered to about 1 kHz by connecting a 100-μΡ capacitor between pins 7 and 8, as shown in Fig. 5-56. Unfortunately, lowering the oscillator fre
quency increases the impedance of both C{ and C2. This can be overcome by in
creasing the values of Cj/C2 by the same factor that the frequency is reduced. For
Figure 5-56· Circuit for lowering oscillator frequency (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-113)
example, if the frequency is decreased by a factor of 10 (10 to 1 kHz), the values of both C, and C2 must be increased by the same factor (from 10 to 100 pF).
5.7.9 Positive Voltage Doubling
Figure 5-57 shows the ICL7660S connected to produce positive voltage dou
bling. In this application the pump inverter switches are used to charge C, to a volt
age level of (V+) - Vp where V* is the supply voltage, and VF is the forward voltage drop of diode Dj.
On the transfer cycle, the voltage on Cj plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2Vp), or twice the supply voltage minus the combined forward voltage drops of diodes Dx and D2. The source impedance of VOUT depends on the output current. For a V+ of 5 V and an output current of 10 m A, the source impedance is about 60 Ω.
5.7.10 Combined Positive and Negative Outputs
Figure 5-58 shows a circuit that combines the functions shown in Figs. 5-51 and 5-57 (negative voltage conversion and positive supply doubling). As an exam
ple, this approach would be suitable for generating +9 V and - 5 V from an existing +5-V supply. In this configuration, capacitors Cj and C3 perform the pump and
ICL7660S
P r
m
γο υ τ - - f - D2 2V*-2Vr
r±T
c< T
NOTE: D1 & D2 can be any suitable diode.
Figure 5-57. Circuit for positive voltage doubling (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-113)
=Γ0!_Γπ
r r>
^r r-
Figure 5-58· Combined negative voltage converter and positive doubler (Harris Semi
conductor, Linear and Telecom ICs, 1991, p. 2-114)
reservoir functions, respectively, for the generation of negative voltage, while ca
pacitors C2 and C4 are pump and reservoir, respectively, for the doubled positive voltage. Note that the source impedances of the generated supplies are somewhat higher because of the finite impedance of the common charge-pump driver at pin 2.
In turn, this reduces available output current for a given output voltage.
5.7.1 ! Voltage Splitting
Figure 5-59 shows how the bidirectional characteristics of the IC can be used to split a higher supply voltage in half. The combined load (RL, RL ) will be evenly shared between the two sides. Because the switches share the load in parallel, the out
put impedance is much lower than in the standard circuits, and higher currents can be drawn.
5.7. Ί2 Regulated Negative Supply Voltage
In some cases, the output impedance of the IC can be a problem, particularly if the load current varies substantially. The circuit of Fig. 5-60 overcomes this prob
lem. A low-power op-amp is used to maintain a constant output voltage. Variations in output voltage (caused by load changes) are fed back to the ICL7660S through
Figure 5-59. Circuit for splitting a power supply (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-114)
100Û J L -T-1 0
VOLTAGE -±T AOJUST ~
Figure 5-60· Circuit for regulating output with variable load (Harris Semiconductor, Linear and Telecom ICs, 1991, p. 2-114)
the op-amp to offset the variations. (Direct feedback, without an op-amp, are not recommended because the ICL7660S output does not respond instantly to changes in input, but only after the switching delay.)
The circuit of Fig. 5-60 supplies enough delay to accommodate the IC while maintaining adequate feedback. An increase in pump and storage or reservoir capac
itor values is recommended. The values shown provide an output impedance of less than 5 Ω to a load of 10 m A.