TYPICAL APPLICATION
of 9 V is above the minimum and well below the maximum of 35/40 V
2. Stability requirements of the internal compensation network
5.11 Switching Regulator
5.11.4 Feedback Pin
The feedback pin is the inverting input of an error amplifier that controls the regulator output by adjusting duty cycle. The noninverting input is internally con
nected to a trimmed 2.21-V reference. Input bias current is typically 0.5 μΑ when the error amplifier is balanced (IOUT = 0). The error amplifier has asymmetrical transconductance for large input signals to reduce start-up overshoot. This makes the amplifier more sensitive to large ripple voltages at the feedback pin. For exam
ple, 100-mVpp ripple at the FB pin creates a 14-mV offset in the amplifier, equiva
lent to a 0.7% output-voltage shift. To avoid output errors, output ripple (pp) should be less than 4% of DC output voltage at the point where the output divider is con
nected.
Figure 5-72 shows how the FB pin is used to downshift the oscillator fre
quency when the regulator output voltage is low. This is done to guarantee that out
put short-circuit current is well controlled, even when duty cycle must be extremely low. The theoretical switch-on time for a buck converter in continuous mode is:
1ON - V + V
v OUT ^ v D
V f VIN l
Figir Λ 5-72· Frequency-shifting connections (Linear Technology, 1991, p. AN44-11)
where
VD = catch diode forward voltage (about 0.5 V) f = switching frequency
At f = 100 kHz, tON must drop to 0.2 μ8 when V ^ = 25 V and the output is shortened (VolJT = 0). In current limit, the LT1074 can reduce tON to a minimum of about 0.6 μ8, much too long to control current correctly for VOUT = 0. To correct this problem, switching frequency is lowered from 100 to 20 kHz as the FB pin drops from 1.3 to 0.5 V. This is done as follows.
As shown in Fig. 5-72, Qj is off when the output is regulating (Vra = 2.21 V).
As the output is pulled down by an overload, VFB eventually reaches 1.3 V, turning on Qj. As the output continues to drop, Q1 current increases proportionately and lowers the oscillator frequency. Frequency-shifting starts when the output is about 60% of normal value, and it is down to the minimum value of about 20 kHz, when the output is 20% of normal value.
The rate at which frequency is shifted is determined by both the internal 3-kQ resistor R3 and the external divider resistors. For this reason, R2 should not be in
creased to more than 4 kQ if the LT1074 is subjected to the simultaneous conditions of high input voltage and output short-circuit.
5.11.5 Vc Pin and Error Amplifier
Figure 5-73 shows the error amplifier and the VC pin (which provides for ex
ternal frequency compensation). As shown, the error amplifier is a single-stage de
sign with added inverters to allow the output to swing above and below the common-mode input voltage.
90μΑ,
^1=<
0•51V
bC 03
04
|90μΑ
Ι»μΑ
J I* I
L C _ 4
EXTERNAL Vc FREQUENCY Q . - , COMPENSATE
300Ω I
—4— I φ ALL CURRENTS SHOWN ARE AT MULL C0N0ITI0N
Figure 5-73. Error amplifier and VC pin (Linear Technology, 1991, p. AN44-16)
One side of the amplifier is tied to a trimmed internal reference voltage of 2.21 V. The other input is brought out as the FB pin. This amplifier has a transcon- ductance or GM (voltage in to current out) of about 5000 microohms. Voltage gain is determined by multiplying GM times the total equivalent output loading, consist
ing of the output resistance of (^ and Q6 in parallel with the series-RC external fre
quency-compensation network.
At DC the external RC is ignored, and with a parallel output impedance for Q4/Q6 of 400 kQ, voltage gain (AV) is about 2000. At frequencies above a few hertz, voltage gain is determined by the external compensation RC and CC, as follows:
AV = at mid-frequencies 6.28 fCC
AV = GM RC at high frequencies.
Phase shift from the FB pin to the VC pin is 90° at mid-frequencies, where the external CC is controlling gain, then drops back to 0° (actually 180° as FB is an in
verting input) when the reactance of CC is small compared to that of RC. The low- frequency "pole" where the reactance of CC is equal to the output impedance of QVQÔ (ro)>is:
f = 1
LPOLE 6.28 rQC where r0 = 400 kQ.
Although fp0LE varies as much as 3 to 1 because of rQ variations, mid-fre
quency gain depends only on GM, which is specified much higher on the data sheet.
The higher-frequency zero is determined solely by RC and CC, as follows:
f ^ E R O
1 6.28 RC CC
The error amplifier has asymmetrical peak-output current. Q3 and Q4 current mirrors are unity gain, but the Q6 mirror has a gain of 1.8 at output null and a gain of 8 when the FB pin is high (Qj current = 0). This results in a maximum positive-out
put current of 140 μΑ and a maximum negative-output (sink) current of 1.1 mA.
The asymmetry is deliberate and results in much less regulator output overshoot during rapid start-up or following the release of an output overload. Amplifier offset is kept low by scaling Qj and Q2 at 1.8:1. Amplifier swing is limited by the internal 5.8-V supply for positive output and by Dj/D2 when the output goes low. Low clamp voltage is about one diode drop (about 0.7 V, - 2 mV/°C).
5.1 ?.6 Power Dissipation
The LT1074 draws about 7.5 mA quiescent current, independent of input volt
age or load, and draws an additional 5 mA during switch-on time. The switch itself
dissipates a power approximately proportional to load current because of finite switch-current rise and fall times.
There is an elaborate equation for calculating the approximate power dissipa
tion for various operating conditions. However, for simplified design, the power dis
sipation is approximately 2.3 W, when VIN = 25 V, VOUT = 5 V, switching frequency = 100 kHz, and IOUT = 3 A.
5.11.7 Positive-to-Negative Converter (Inverter)
Figure 5-74 shows the LT1074 used to generate a 5-V from an input of +4.75 to 40 V. The circuit will work if the sum of the input and output voltage is greater than the 8-V minimum supply voltage specification and the minimum positive sup
ply is +4.75 V.
The ground pin of the IC is connected to the negative output. This allows the feedback divider R3/R4 to be connected in the normal fashion. If the ground pin is tied to ground, some level shift and inversion is required to generate the proper feed
back signal.
Positive-to-negative converters are sometimes difficult to stabilize, especially with low input voltages. R,, R2, and C4 are added to the basic design solely to guar
antee feedback-loop stability at low input voltage. These components can be omit-
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' LOWER REVERSE VOLTAGE RATING MAY BE USED FOR LOWER INPUT VOLTAGES.
LOWER CURRENT RATING IS ALLOWED FOR LOWER OUTPUT CURRENT.
" LOWER CURRENT RATING MAY BE USEO FOR LOWER OUTPUT CURRENT.
* R1. R2. ANO C4 ARE USEO FOR LOOP FREQUENCY COMPENSATION. BUT R1 AND R2 MUST BE INCLUDED IN THE CALCULATION FOR OUTPUT VOLTAGE DIVIDER VALUES.
FOR HIGHER OUTPUT VOLTAGES, INCREASE R1. R2 ANO R3 PROPORTIONATELY;
Μ-νουτ-^οαϊ)
RI - ( R 3 ) (1.86) R2>(R3)(3.65)
' ' * MAXIMUM OUTPUT CURRENT OF 1A IS DETERMINED BY MINIMUM INPUT VOLTAGE OF 4.5V. HIGHER MMfMUM INPUT VOLTAGE WILL ALLOW MUCH HIGHER OUTPUT CURRENTS.
Figure 5-74. Positive-to-negative converter (Linear Technology, 1991, p. AN44-28)
ted where VIN is greater than 10 V or when VIN/V0UT is greater than 2. Rj plus R2 is in parallel with R3 for DC output voltage calculations. Use the following guidelines for these resistors:
R4=1.8kQ
R3 = VOUT -2.37 (in 1<Ω) R1=R3(1.86)
R2 = R3 (3.65)
If Rj and R2 are omitted:
R4 = 2.1kQ
R3 = VOUT-2.21(inkQ).
A +12 to -5-V converter (without R,/R2) would have R4 = 2.21 kQ and R3 = 2.79 kQ. Recommended compensation components would be C3 = 0.005 μΡ in par
allel with a series RC of 0.1 μΡ and 1 kQ.
The circuit of Fig. 5-74 works by charging Lj through the input voltage when the LT1075 switch is on. During switch-off time, the inductor current is diverted through Dj to the negative output. For continuous mode operation, the duty cycle of the switch is (use an absolute value for V0UT):
D C = OUT V + V v V IN ^ v OUT The peak switch current for continuous mode is:
__ IQUT(V IN + v OUT) vv JN) (VOUT) SW(PEAK) y/ ' Ofifv" + V V
v IN Z 1M v IN + v O U T;
To calculate maximum output for a given maximum switch current (IM), the equation can be rearranged to (use a minimum value for VIN):
T _ V'lN-aMHRL) Γτ ( V W C V Q U T ) 1
W A X , "
VjN +Y
omL^^fLiVV + V ^ J -
Note that an extra term (IMRL) has been added to account for the series resis
tance RL of the inductor, which may become a significant loss at low input voltages.
Maximum output current depends on input and output voltage, unlike a buck converter, which will supply essentially a constant output current. The circuit shown in Fig. 5-74 will supply over 4 A at V^ = 30 V, but only 1.3 A at VIN = 5 V. The IOUT equation does not include second-order loss terms such as capacitor ripple cur
rent, switch rise and fall time, core loss, and output filter. These factors may reduce maximum output current by up to 10% at low input and/or output voltages.
Figure 5-75 shows IOUT(MAX) versus input voltage for various output voltages.
The values in Fig. 5-75 assume a 25-μΗ inductor for VOUT = -5 V, 50-μΗ for VOUT
= -12 V, and 100-μΗ for VOUT = -25 V.
10 20 30 INPUT VOLTAGE (V)
Figure 5-75· Maximum output current versus input voltage (Linear Technology, 1991, p. AN44-29)
If absolute minimum circuit size is required and load currents are not too high, the discontinuous mode can be used. The minimum inductance required for a speci
fied load is (discontinuous mode):
"MIN
^ O U T ^ OUT/)
dM)2f
A maximum load current that can be supplied in the discontinuous mode.
Above this current, the equation for LiM is not valid. Maximum load current in dis
continuous mode (discontinuous mode; use a minimum value for VJN):