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TYPICAL APPLICATION

of 9 V is above the minimum and well below the maximum of 35/40 V

2. Stability requirements of the internal compensation network

5.11 Switching Regulator

5.11.7 Block Diagram Description

As shown in Fig. 5-69, the switch cycle is initiated by the oscillator setting the R/S latch. The pulse that sets the latch also locks out the switch through gate Gr

The effective width of this pulse is about 700 ns, which sets the maximum switch duty cycle to about 93% at 100 kHz switching frequency.

Figure 5-70. Electrical characteristics and package data (L ABSOLUTE

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RATIÎIGS Input Voltage LT1074/LT1076 45V LT1074HV/76HV 64V Switch Voltage with Respect to Input Voltage ΙΛ1074/76 64V LT1074HV/76HV 75V Switch Voltage with Respect to Ground Pin (V$w Negative) LT1074/76(Note6) 35V LT1074HV/76HV (Note 6) 45V Feedback Pin Voltage -2V, +10V Shutdown Pin Voltage (Not to Exceed V!N) 40V Status Pin Voltage 30V (Current Must Be Limited to 5mA When Status Pin Switches "On") Complementary Output Voltage 30V (Current Must Be Limited to 20mA When Output Switches "On") ILIMn Voltage (Forced) 5.5V EXTLIM Pin Voltage VIN -2V to V,N +0.4V Freq Pin Voltage 5.5V Maximum Operating Ambient Temperature Range LT1074C/76C, LT1074HVC/76HVCC to 70°C LT1074M/76M, LT1074HVM/76HVM ..-55°C to 125°C Maximum Operating Junction Temperature Range LT1074C/76C, LT1074HVC/76HVCC to 125°C LT1074M/76M, LT1074HVM/76HVM...-55°Cto 150°C Maximum Storage Temperature -65°C to 150°C 5J Lead Temperature (Soldering, 10 sec.) 300°C

Inear Technology, 1991, p. AN44-3-4)

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FRONT VIEW LEAOS ARE FORMED STANDARD FOR STRAIGHT LEAOS OROER FLOW 06 BOTTOM VIEW O; CASEISGNO

ORDER PART NUMBER LT1074CT LT1074HVCT LT1076CT LT1076HVCT LT1074MK LT1074HVMK LT1074CK LT1074HVCK LT1076MK LT1076HVMK LT1076CK LT1076HVCK LT1074CV LT1074HVCV LT1076CV LT1076HVCV

Figure 5-70. (continued)

€l€CTRICA L CHARACTERISTIC S τ ,

= 25=C, V|N = 25V, unless otherwise noted. PARAMETER Switch "On" Voltage (Note 1) Switch 'Off" Leakage Supply Current (Note 2) Minimum Supply Voltage Switch Current Urrot (Note 4) Maximum Duty Cycle Switching Frequency Switching Frequency Une Regulation Error Amplifier Voltage Gain (Note 6) Error Amplifier Transconductance Error Amplifier Source and Sink Current Feedback Pin Bias Current CONOITIONS LT1074 Isw.lA.T^Q/C lsw1A.T,<03C l$w»5A.T,>0'C Isw» 5A. T, < 0"-C LT1076 lS0 5A ISW«2A LT1074 V,Ns25V.VSWzO VIN»VMAX Vsw*0(Note7) LT1076 V,N » 25V. Vsw = 0 VIN-VMAX VSw = 0(Note7) VFB»2 5V.V,NS40V 40V<V,N<60V VSHUT * 0.1V (Oevice Shutdown) (Note 8) Normal Mode Startup Mode (Not· 3) LT1074 lUM0pen RUM « 10k (Note 5) RUM« 7k (Note 5) LT1076 IHM Open RUM »10k (Note 5) RUM >7k (Note 5) T,^125-C T, > 125°C VFB*0V through 2kn (Note 4) 8VsV,MsVMAx(Note7) 1V<VCS4V Source (VfB * 2V) Sink (VFB» 2.5V) VFB«VREF

• • • • • • • • •

MIN

TYP MAX | 18 2.1 2.3 2.5 | 1.2 1 1.7 - I 5 10 300 500 150 250 | 5.5 2 85 90 85 85

8.5 9 140 7.3 35 65 45 3 26 18 1.2 90 100 20 003

11 I 12 300 8 47 8.5 3.2 110 120 125 01 2000 3700 100 07

5000 140 1 0.5

8000 225 16 2

1

1

[ A ! A

1 1 1

! kH 1 kH | %/ | V/ < μίπη | u 1 m I u

€l€CTBICfll CHBBRCTCBIST1CS T|.250 C,Vw.2SY,unlfttot»rwlienottd. PAJUMCTER Reference Voltage Reference Voltage Tolerance Reference Voltage Line Regulation VC Vortage at 0% Duty Cycle Multiplier Reference Voltage Shutdown Pin Current Shutdown Thresholds Status Window Status High Level Status Low Level Status Delay Time Status Minimum Width Freq Pin Voltage COMOUT Saturation Voltage COMOUT Leakage Thermal Resistance Junction to Case

commons VC«2V Vfw (Nominal) » 2.21V All Conditions of Input Voltage. Output Voltage. Temperature and Load Current 8V*V,NsVMAx(Note7) Over Temperature VSH-5V VSMSVTH«SHOIO(S2.5V) Switch Duty Cycle * 0 Fully Shut Down As a Percent of Feedback Voltage •STATUS* 10utsourcing 'STATUS * 1 6*"* Sinking RfAEO«15k •SINK »10mA VCOMOUT » 30V LT1074 LT1076

• • • • • • • •

MM TYP MAX 2155 221 2265 ±05 ±1.5 ±1 ±2.5 0.005 0.02 1.5 -4 24 5 10 20 50 2 2 2.45 2 7 01 0.3 0.5 4 ±5 6 ! 3 5 4 5 5.0 I V 025 0.4 9 30 1.55 0.5 1 50 2.5 4.0

Figure 5-70. (continued) The · denotes the specifications which apply over the full operating temperature range. Note 1: To calculate maximum switch "on" voltage at currents betwee low and high conditions, a linear interpolation may be used. Note 2; A feedback pin voltage (VFB) of 2.5V forces the Vç pin to its lo clamp level and the switch duty cycle to zero. This approximates the zer load condition where duty cycle approaches zero. Note 3: Total voltage from VIN pin to ground pin must be > 8V after startup for proper regulation. Note 4: Switch frequency is internally scaled down when the feedbac voltage is less than 1.3V to avoid extremely short switch on times. Durin testing, VFB is adjusted to give a minimum switch on time of 1μ$. Note 5: lUM - RuM ~1k (LT1074). IUM = RuM ~1k (LT1076). cK DDK Note 6: Switch to input voltage limitation must also be observed. Note 7: VMAX = 40V for the LT1074/76 and 60V for the LT1074HV/76H Note 8: Does not include switch leakage.

The switch is turned off by comparator Cj that resets the latch. Cj has a saw­

tooth waveform as one input, and the output of an analog multiplier as the other input. The multiplier output is the product of an internal reference voltage, and the output of the error amplifier Ap divided by the regulator input voltage. In standard buck regulators, this means that the output voltage of Αχ required to keep a constant regulated output is independent of regulator input voltage. This greatly improves line transient response and makes loop gain independent of input voltage.

The error amplifier is a transconductance (GM) type with a GM at null of about 5000 μπιΐιο. Slew current going positive is 140 μΑ, and negative slew current is about 1.1 mA. This asymmetry helps prevent overshoot on start-up. Overall loop frequency compensation is provided by a series RC network from VC to ground.

Switch current is continuously monitored by C2, which resets the R/S latch to turn the switch off if an overcurrent condition occurs. The time required for detec­

tion and switch turn-off is about 600 ns. So minimum switch-on time (in current limit) is 600 ns.

Under dead-shorted output conditions, switch duty cycle may be as low as 2%

to maintain control of output current. This would require a switch-on time of 200 ns at 100 kHz switching frequency, so the frequency is reduced at very low output volt­

ages by feeding the feedback (FB) signal into the oscillator and creating a linear fre­

quency-downshift when the FB signal drops below 1.3 V.

The switch used in the LT1074 is a Darlington NPN (single NPN for LT1076) driven by a saturated PNP. Special patented circuitry is used to drive the PNP on and off very quickly even from the saturation state. This switch configuration has no

"isolation tabs" connected to the switch output, which can therefore swing to 40 V below ground.