57
This result is also confirmed by the ‘.meas’ directive shown in the LTspice schematic. From the error log file, we find ‘w: 1/i1#input_impedance=1m AT 2.78074e-005’ and with the channel width speci- fied to be a multiple of 1 µm, we selectW1=28 µm.
WithW1=28 µm, the common-source amplifier is shown in the figure below with a specification for a
‘.dc’ simulation. From the resulting simulation, we find an input bias voltage ofVIN=0.773 V for an output bias voltage of 1.5 V. This value is also confirmed by the ‘.meas’ directive shown in the schematic.
From the error log file, we find ‘vbias: v(vout)=1.5 AT 0.773027’.
With the bias value forVininserted and with an ac amplitude of 1 V forVin, a ‘.ac’ simulation will show both the gain at low frequencies and verify the gain-bandwidth product of 50 MHz. The figure below shows the schematic and the resulting simulation plot. From the plot, we find a low-frequency gain of 38.1 dB and a unity-gain bandwidth of 49.8 MHz. Since the phase shift at the unity-gain bandwidth is only about 90°, the unity-gain bandwidth is a very good approximation to the gain-bandwidth product GBW.
We may also find the low-frequency gain and the gain-bandwidth product using the ‘.meas’ directives shown in the schematic. From the error log file, we find ‘lfgain: mag(v(vout))=(38.0736dB,0°) at 10000’ and ‘gbw: mag(v(vout))=1 AT 4.98319e+007’.
59
Problem 4.2
VDD=VSS=1.5 V,L1=L2=1 µm CL=0.5 pF,RL=10 kΩ
For the inverting amplifier shown above, design M1and M2so that the dc bias value of the output voltage is within the range±100 mV with an input dc bias voltage of 0 V and so that the low-frequency small- signal gain with an input dc bias voltage of 0 V is−10 V/V. Use the BSIM3 transistor models shown in Fig. 3.10 and use a channel length ofL1=L2=1 µm. Use channel widths for M1and M2which are multiples of 0.5 µm. What is the low-frequency small-signal gain if the load resistorRLis omitted?
What is the gain-bandwidth product of the amplifier forRL=10 kΩand forRL=∞?
Figure 3.10 may be found in the Introduction of this book.
Solution:
We start the solution by finding a ratio between the channel widths for the NMOS transistor (M1) and the PMOS transistor (M2). For this, we may run a simulation as shown below where the channel widths are defined as parameters.
59
Download free eBooks at bookboon.com
The widthW1is selected to be 10 µm while the widthW2is stepped from 2W1(20 µm) to 4W1(40 µm).
From a ‘.op’ simulation, the output voltage is plotted versusW2. The simulation plot shows that with W1=10 µm,W2should be 32.1 µm in order to obtain an output voltage of 0 V. This value is confirmed by the ‘.meas’ directive shown in the schematic where the error log file reports ‘w2: v(vout)=0 AT 3.21396e-005’. Thus, the ratio betweenW2andW1is 3.21.
Next, we define the parameterW2to be 3.21 times the parameterW1and we step the parameterW1over a suitable range (5 µm to 15 µm) and run a ‘.tf’ simulation in order to find the low-frequency gain as a function ofW1, see figures below. From the simulation plot, we find that in order to obtain a gain of
−10 V/V,W1should be 6.28 µm. This value is confirmed by the ‘.meas’ directive shown in the schematic where the error log file reports ‘w1: transfer_function=-10 AT 6.28311e-006’. Nearest multiple of 0.5 µm isW1=6.5 µm, and with this value ofW1, we findW2=3.21W1=20.87 µm. Rounding off to nearest multiple of 0.5 µm givesW2=21 µm.
WithW1=6.5 µm andW2=21 µm, we run a ‘.op’ simulation to verify the bias value of the output voltage and a ‘.tf’ simulation to verify the gain.
The outputs of these simulations are shown below, and we find the underlined results for gain and output bias voltage reasonably close to the design targets.
Output file, .op simulation Output file, .tf simulation
For finding the low-frequency gain whenRL is omitted, we run a ‘.tf’ simulation whereRL is discon- nected. This results in a transfer function of−42.6574, i.e., a low-frequency gain of 32.6 dB.
61
For finding the gain-bandwidth product, we run a ‘.ac’ simulation from 100 kHz to 1 GHz and find the bandwidth BW using the following ‘.meas’ directives: ‘.meas LFgain find mag(V(Vout)) at 100k’ and ‘.meas BW when mag(V(Vout))=LFgain/sqrt(2)’.
With RL included, the error log file reports BW=39.2602 MHz, giving a gain-bandwidth product of 403.8 MHz. WithRLomitted, the error log file reports BW=9.44533 MHz, giving a gain-bandwidth product of 402.9 MHz.
In order to verify that the ‘.ac’ simulation runs from a reasonable bias point, also whenRL=∞, a ‘.op’
simulation withRLomitted may be run. The output file from this simulation shows an output voltage of 85.698 mV, i.e, less than 100 mV as requested.
We may verify these results from a plot resulting from a ‘.ac’ simulation withRLstepped between two values, 10 kΩand 10 GΩ. From the plot shown below, we find that withRL=∞ (10 GΩ), the low- frequency gain is 32.6 dB (or−42.7 V/V), and we notice that at high frequencies (>100 MHz), the response is almost independent ofRLwith a unity-gain bandwidth of approximately 400 MHz.
The unity-gain bandwidth is slightly smaller than the gain-bandwidth product. A close examination of the Bode plot reveals that the phase ofVohas shifted more than 90° at the unity-gain frequency, and this is an indication that the amplifier has higher-order pole(s) which cause an additional attenuation of the output voltage so that the unity-gain frequency is smaller than the gain-bandwidth product.
61
Download free eBooks at bookboon.com
Problem 4.3
L1=L2=L3=L4=L5=L6=L7=L8=0.35 µm RL=10 kΩ,VDD=VSS=1.5 V
The figure above shows a class AB buffer amplifier. Design the output transistors M1 and M2 so that the amplifier can deliver an output-voltage swing of±0.5 V with a load resistor of 10 kΩ. Assume that the gate voltage of M1 and M2 can reach the positive and negative supply voltages, respectively. Select values of the channel widths which are multiples of 10 µm. Use the BSIM3 transistor models shown in Fig. 3.10.
Design the bias network M3 −M8 andRB to provide a bias current of 1 µA for M3 −M8. M5−M8
should be designed to have a saturation voltage|VDSsat|of less than 50 mV, and the channel widths should be multiples of 10 µm. M3and M4should be scaled to channel widths of 0.1 times the channel widths of M1and M2, respectively.
Plot the output voltage versus the input voltage for−1.5 V <vIN < 1.5 V. Find the open-circuit voltage gain and the output resistance of the buffer for an input bias voltage of 0 V. Find the bias current in M1
and M2for an output bias voltage ofVO=0 V. Why is the current scaling in M1−M2/ M3−M4different from the channel width scaling?
Figure 3.10 may be found in the Introduction of this book.
Solution:
For finding the channel widthW1, we run a ‘.op’ simulation on a single NMOS transistor with gate, source, drain and bulk connected to voltages resulting in the highest value of output voltage. Using a
‘.step param’ directive, the output voltage is simulated versus the channel width.
The following figure shows the schematic and the simulation plot from which we findW1=30 µm (using multiples of 10 µm) in order to achieve an output voltage of +0.5 V.
63
The channel widthW2 is found in the same way asW1, running a ‘.op’ simulation on a single PMOS transistor with gate, source, drain and bulk connected to voltages resulting in the lowest value of output voltage.
The following figure shows the schematic and the simulation plot from which we findW2 =240 µm (using multiples of 10 µm) in order to achieve an output voltage of−0.5 V.
For the bias network, M3and M4are designed by scalingW1andW2by a factor of 0.1, respectively. This givesW3=3 µm andW4=24 µm.
The transistors M5- M8should have a saturation voltage of less than 50 mV for a drain current of 1 µA.
For the PMOS transistors (M5 and M6), the channel width is found from the simulation shown in the figure below. The simulation is run with different values ofW5in multiples of 10 µm and the smallest value ofW5resulting in|Vdsat|< 50 mV (listed in the error log file) is selected, i.e.,W5=W6=30 µm.
Error log file
63
Download free eBooks at bookboon.com
For the NMOS transistors (M7 and M8), the channel width is found from the simulation shown in the figure below. The simulation is run with different values ofW7in multiples of 10 µm and the smallest value ofW7resulting inVdsat< 50 mV is selected, i.e.W7=W8=10 µm.
Error log file
With all transistor dimensions in place, the complete schematic can be drawn as shown below. Notice that the dc value of the input voltage is defined as a parameter ‘VINbias’. For the initial simulations, this is defined to have a value of 0. The only device still to be designed is RB. This can be found from a ‘.op’ simulation with RB stepped over a suitable range. From the directive ‘.meas RB when I(RB)=1u’ we find thatRB=1.83892 MΩresults in a bias current of 1 µA forRB, M6and M8, so for the following simulations, we define ‘.param RB=1.83892e6’ and change the ‘.step param RB’ directive into a comment.
Next, a ‘.dc’ simulation is run, resulting in the following simulation plot. We notice that the buffer amplifier can deliver an output swing of±0.5 V and that the gain is slightly smaller than 1.
65
For finding the open-circuit voltage gain and output resistance for an input bias voltage of 0 V, we run a ‘.tf’ simulation with ‘RL’ disconnected. The output file is shown below, and we findAvoc=0.95 V/V andro=1005Ω.
Output file
For finding the bias currents in M1and M2 for an output voltage of 0 V, we first need to find the value of the input dc voltage which results in an output voltage of 0 V. For this, we use the directive ‘.meas VINbias when v(VO)=0’ (shown as a comment in the LTspice schematic) and run a ‘.dc’ simulation.
Use a small increment size (1 mV) for the ‘.dc’ simulation in order to get a reasonably precise result from the ‘.meas’ directive. From the error log file, we find that an input voltage of 4.77052 mV re- sults in an output voltage of 0 V, so we redefine VINbias to this value using the directive ‘.param VINbias=4.77052m’. With this value ofVINbias, we run a ‘.op’ simulation, and the error log file from this gives all the transistor bias currents as shown below.
Error log file
65
Download free eBooks at bookboon.com
We notice that the current scaling in M1- M2/ M3- M4is larger than the channel width scaling. This is caused by the larger|VDS|values for M1- M2than for M3 - M4, by the input offset voltage, and by the smaller threshold voltages for M1- M2than for M3- M4.
Problem 4.4
L1=L2=1 µm,W1=W2=10 µm IB=20 µA,VB=1.5 V,VDD=3 V.
NMOS model parameters:Kp=190 µA/V2,Vto=0.57 V,λ=0.16 V−1,γ=0.50√
V,|2ΦF|=0.7 V.
For the telescopic cascode shown above, find the bias value ofVIN required to give an output voltage of 2 V. Also find the small-signal gainAvocand output resistanceroat low frequencies. Find the small- signal resistancerx to ground from the nodexbetween the source of M2 and the drain of M1. Use the Shichman-Hodges transistor model with the parameters listed above.
Solution:
The figure below shows the cascode stage with a specification for a ‘.dc’ simulation. Also shown is the resulting plot of the output voltage. Apparently, the simulation generates unrealistically high output voltages, several MV. This is due to the fact that the drain of M2 is connected directly to an ideal dc current source.
67
In order to seeV(vo)in a realistic range of output voltages, we set the range of the y-axis to 3 V, either by the command ‘Plot Settings→ Manual Limits’ or by moving the cursor to the y-axis and using a right-click on the mouse. The resulting plot is shown below, left plot. We see that the output voltage changes abruptly for an input voltage of about 0.7 V, and in order to find the exact input voltage, we zoom in on a small part of the plot, see right plot below. From this, we findVIN=708.21 mV. You will find that it is very difficult to place the cursor corresponding to an output voltage of exactly 2.00 V. Notice also that the value ofVINhas been specified with a resolution exceeding the increment size in the ‘.dc’
command, so it is based on an interpolation.
An alternative way to find the bias value ofvIN is to use the following ‘.meas’ directive: ‘.meas VIN when v(VO)=2’. From the error log file, we find ‘vin: v(vo)=2 AT 0.708209’, matching the value found from the simulation plot very well.
In order to verify the bias point, we run a ‘.op’ simulation with a dc value ofVINspecified to 708.209 mV.
The output file from this is shown below, and we see thatV(vo)is sufficiently close to 2 V.
Output file
With the bias point in place, the small-signal gainAvoc and output resistancero at low frequencies are found from a ‘.tf’ simulation withV(VO)as the output andVINas the source. The following figure shows the output file from this simulation. From this, we find a gain of−14104 V/V or 83 dB and an output resistance of 49 MΩ.
67
Download free eBooks at bookboon.com
Output file
For finding the small-signal resistancerx to ground from the node xbetween the source of M2 and the drain of M1, we run a ‘.tf’ simulation withV(Vx)as the output andVINas the source. The output file from this ‘.tf’ simulation is shown below. From this, we find a resistancerx of 344 kΩ.
Output file
Problem 4.5
L1=L2=1 µm,W1=10 µm,W2=30 µm IBP=40 µA,IBN=20 µA,VB=1.5 V,VDD=3 V.
NMOS model parameters:Kp=190 µA/V2,Vto=0.57 V,λ=0.16 V−1,γ=0.50√
V,|2ΦF|=0.7 V.
PMOS model parameters:Kp=55 µA/V2,Vto=−0.71 V,λ=0.16 V−1,γ=0.75√
V,|2ΦF|=0.7 V.
For the folded cascode shown above, find the bias value ofVIN required to give an output voltage of 1 V. Also find the small-signal gain Avoc and output resistancero at low frequencies. Find the small- signal resistancerx to ground from the nodexbetween the source of M2 and the drain of M1. Use the Shichman-Hodges transistor model with the parameters listed above.
69
Solution:
The figure below shows the folded-cascode stage with a specification for a ‘.dc’ simulation. Also shown is the resulting plot of the output voltage. Apparently, the simulation generates unrealistically high output voltages, several MV. This is due to the biasing by two ideal dc current sources. You may also notice that the simulation time is quite long, and examining the error log file, you find that LTspice has some challenges in finding the operating points for the values of input voltage giving unrealistic values of output voltage.
In order to seeV(vo)in a realistic range of output voltages, we set the range of the y-axis to 3 V, either by the command ‘Plot Settings→ Manual Limits’ or by moving the cursor to the y-axis and using a right-click on the mouse. The resulting plot is shown below, left plot. We see that the output voltage changes abruptly for an input voltage of about 0.7 V. Even when zooming in on a small part of the plot, it is difficult to find the value ofVIN resulting in an output voltage of 1 V, so in order to improve the accuracy, we run a ‘.dc’ simulation from 690 mV to 694 mV with a step size of 1 µV. From this, we find VIN=693.68485 mV.
An alternative way to find the bias value ofvIN is to use the following ‘.meas’ directive: ‘.meas VIN when v(VO)=1’. From the error log file, we find ‘vin: v(vo)=1 AT 0.693684’, matching the value found from the simulation plot very well.
69
Download free eBooks at bookboon.com
In order to verify the bias point, we run a ‘.op’ simulation with a dc value ofVINspecified to 693.684 mV.
The output file from this is shown below, and we see thatV(vo)is sufficiently close to 1 V, and also the voltage at the intermediate nodexhas a reasonable value within the supply voltage range.
Output file
With the bias point in place, the small-signal gainAvoc and output resistancero at low frequencies are found from a ‘.tf’ simulation with V(VO) as the output and VIN as the source. The output file from this ‘.tf’ simulation is shown below. From this, we find a gain of−15109 V/V or 84 dB and an output resistance of 47 MΩ.
Output file
For finding the small-signal resistancerx to ground from the node xbetween the source of M2 and the drain of M1, we run a ‘.tf’ simulation withV(Vx)as the output andVIN as the source. The output file from this ‘.tf’ simulation is shown below. From this, we find a resistancerxof 430 kΩ.
Output file
71
Problem 4.6
The figure above shows an alternative version of the LTspice schematic from Fig. 4.23 with a different arrangement for the input voltages. Define the ac amplitudes of ‘VCM’, ‘V1’, ‘V2’ and ‘VDD’ such that the ‘.ac’ simulation shows the differential gain and compare your simulation to Fig. 4.27. Next, define the ac amplitudes of ‘VCM’, ‘V1’, ‘V2’ and ‘VDD’ such that the ‘.ac’ simulation shows the common-mode gain and compare your simulation to Fig. 4.28. Finally, define the ac amplitudes of ‘VCM’, ‘V1’, ‘V2’
and ‘VDD’ such that the ‘.ac’ simulation shows the power-supply rejection and compare your simulation to Fig. 4.29.
For convenience, Fig. 4.23 is shown below.
Figure 4.23:LTspice schematic for simulations of a PMOS differential pair with NMOS active load.
71
Download free eBooks at bookboon.com
Solution:
For the differential gain, we define the ac amplitudes in the alternative LTspice schematic as follows:
VCM: AC Amplitude = 0, V1: AC Amplitude = 0.5, V2: AC Amplitude = 0.5, VDD: AC Amplitude = 0.
The resulting schematic and simulation plot is shown below. The simulation plot is identical to Fig. 4.27 in ‘CMOS Integrated Circuit Simulation with LTspice’.
73
For the common-mode gain, we define the ac amplitudes as follows:
VCM: AC Amplitude = 1, V1: AC Amplitude = 0, V2: AC Amplitude = 0, VDD: AC Amplitude = 0.
The resulting schematic and simulation plot is shown below. The simulation plot is identical to Fig. 4.28 in ‘CMOS Integrated Circuit Simulation with LTspice’.
73
Download free eBooks at bookboon.com
For the power supply rejection, we define the ac amplitudes as follows:
VCM: AC Amplitude = 0, V1: AC Amplitude = 0, V2: AC Amplitude = 0, VDD: AC Amplitude = 1.
The resulting schematic and simulation plot is shown below. The simulation plot is identical to Fig. 4.29 in ‘CMOS Integrated Circuit Simulation with LTspice’.
75
Problem 4.7
L1=L2=L3=L4=L5=1 µm
W1=30 µm,W2=33 µm,W3=W4=W5=W6=10 µm
AD1=AS1=AD2=AS2=30(µm)2,AD3=AS3=AD4=AS4=AD5=AS5=AD6=AS6=10(µm)2 PD1=PS1=PD2=PS2=32 µm,PD3=PS3=PD4=PS4=PD5=PS5=PD6=PS6=12 µm RB=100 kΩ,CL=0.5 pF,VDD=3.0 V,VCM=1 V
.MODEL NMOS-SH nmos (Kp=190u Vto=0.57 Lambda=0.16 Gamma=0.50 Phi=0.7 +TOX=8n CGSO=0.28n CGBO=1p CGDO=0.28n CJ=1m CJSW=0.4n)
.MODEL PMOS-SH pmos (Kp=55u Vto=-0.71 Lambda=0.16 Gamma=0.75 Phi=0.7 +TOX=8n CGSO=0.21n CGBO=1p CGDO=0.28n CJ=1.5m CJSW=0.4n)
For the differential pair shown above, we assume that a layout error has resulted in a mismatch between M1 and M2 such thatW1=30 µm andW2=33 µm. Find the input offset voltage caused by this error for a common-mode input voltage ofVCM =1 V and an output voltage of 0.7 V. Use the Shichman- Hodges transistor models shown above. Next, plot the differential gain and the common-mode gain versus frequency. Find the gain-bandwidth product and calculate the common-mode rejection ratio at low frequencies. Also plot the gain from the power supply to the output and calculate the power-supply rejection ratio at low frequencies.
Solution:
The following figure shows the schematic in LTspice. For finding the offset voltage, we use a ‘.dc’
simulation with the input voltageV1to the noninverting input as the source to sweep. Using the ‘.meas’
directive shown in the schematic, we find from the error log file thatVoff=−4.2 mV results in an output voltage of 0.7 V.
75
Download free eBooks at bookboon.com