Problem 5.1
Rs=1 MΩ,VDD=3 V,C1=0.2 pF,Cc=0.7 pF,CL=1.5 pF.
An inverter as shown in Fig. 5.25 may be used as an inverting amplifier. Design a test bench as shown in the figure above using a supply voltage of 3 V, a minimum length of ‘Lmin=0.35u’, a fanout of
‘Fanout=1’ and the BSIM3 transistor model from Fig. 3.10.
Find an input bias voltageVBwhich gives an output bias voltage of 1.5 V. With this value ofVB, simulate the ac response and find the low-frequency gain and the dominant pole. Also, use the Miller approxima- tion (Bruun 2019, Chan Carusone, Johns & Martin 2012) to calculate the dominant pole and compare to the simulated value.
For convenience, Fig. 5.25 is shown below. Figure 3.10 may be found in the Introduction of this book.
Figure 5.25:Inverter, schematic and symbol.
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Solution:
The figure below shows the schematic drawn in LTspice. For finding the bias input voltage, we run a ‘.dc’ simulation, the result of which is also shown below. From this, we find that a bias voltage of VB=1.505 V results in an output voltage of 1.5 V. We may also use the directive ‘.meas dc VB when v(Vo)=1.5’ shown in the schematic to verify the value ofVB. Notice that this ‘.meas’ directive specifies
‘.meas dc’, i.e., it is only used after a ‘.dc’ simulation. When specifying the simulation type in the
‘.meas’ directive, you avoid a message in the error log file about a failed measurement when running a simulation which is incompatible with a ‘.meas’ directive.
From the error log file, we findVB=1.50496 V.
With 1.505 V inserted as the dc value forVin, we run a ‘.ac’ simulation from which we find a low- frequency gain of 24.9 dB (orAv=−17.6 V/V). With the capacitorsC1,CcandCLall being much larger than the parasitic transistor capacitances, it can be assumed that the dominant pole can be found as the
−3 dB frequency, and from the following simulation plot, we find a dominant-pole frequency of 12 kHz.
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We may also include the directive ‘.meas ac Av find mag(v(Vo)) at 100’ for finding the low- frequency gain and the directive ‘.meas ac fp when mag(v(Vo))=Av/sqrt(2)’ for finding the dom- inant pole. Notice that these ‘.meas’ directive specifies ‘.meas ac’, i.e., they are only used after a ‘.ac’
simulation. From the error log file, we findAv=24.8838 dB∼ −17.6 V/V and fp=11.966 kHz.
A calculation of the dominant-pole frequency gives fp= (2πRs((1−Av)Cc+C1))−1=12 kHz.
Problem 5.2
Simulate the ac response of the closed-loop gain and the loop gain for the opamp shown in Figs. 5.10 and 5.11 withC1=1 pF,C2=0.2 pF andCL=1.5 pF using the generic filter blocks from Table 5.3.
Assume the following transfer function for the opamp:
Av(s) =ωta(1−s/ωz) s(1+s/ωp2)
whereωta=2π×120 MHz,ωz=2π×200 MHz andωp2=2π×76 MHz.
Find the phase margin and the closed-loop bandwidth and compare to the results found in Example 5.2.
For convenience, Figs. 5.10, 5.11 and Table 5.3 are shown below.
Figure 5.10:Inverting opamp configuration with capacitive feedback.
Figure 5.11:Open loop circuit for finding the loop gainL(s) =Vr(s)/Vt(s).
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Transfer
function Schematic Symbol Parameter
Zero in 0 T(j f) =j f/ft
Unity-gain frequencyft
Real zero T(j f) = 1+j f/fz
Zero frequencyfz
Pole in 0 T(j f) =ft/(j f)
Unity-gain frequencyft
Real pole T(j f) =
1+j f1/fp
Pole frequencyfp
Lowpass biquad T(j f) =
1+(j f/f0)/Q+(1 j f/f0)2
Resonance frequencyf0 and quality factorQ Table 5.3:Generic filter blocks defined as subcircuits.
Solution:
The opamp transfer function includes a factor with a pole in 0, a factor with a real pole and a factor with a real zero. The corresponding filter blocks from Table 5.3 in ‘CMOS Integrated Circuit Simulation with LTspice’ areLP0,LP1andHP1.
The figure below shows the LTspice schematic corresponding to Fig. 5.10 with these filter blocks inserted for the opamp and with parameters as specified in Problem 5.2. Note that the filter blockHP1has a right half plane zero, so the parameterfzmust be specified as a negative frequency. In order to provide an inverting input for the opamp, an inversion is obtained from the voltage controlled voltage sourceE1.
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For finding the closed-loop ac response, we run a ‘.ac’ simulation and the result of this is shown be- low. From the plot, we find a closed-loop bandwidth of 30.5 MHz. This is higher than the bandwidth found in Example 5.2 because higher order poles and zeros are neglected when using the opamp transfer function specified in Problem 5.2.
The error log file opens automatically after running the simulation because some floating nodes in the circuit generate error messages. However, since LTspice assumes a bias voltage of 0 V for these floating nodes, the simulations are not compromised. The error messages can just be ignored. You may prevent LTspice from automatically opening the error log file because of these warnings and errors by including the directive ‘.options topologycheck=0’.
With the ‘.meas’ directives shown in the schematic, the error log file reports a low-frequency gain of 13.9794 dB and a bandwidth of 30.6363 MHz. These values closely match the values found from the plot below.
The following figure shows the LTspice schematic corresponding to Fig. 5.11.
For finding the loop gain ac response, we run a ‘.ac’ simulation. Again, the error log file opens auto- matically after running the simulation because of some floating nodes in the circuit. From the plot, we find a phase margin of 180° −110° =70°. This is more than the phase margin found in Example 5.2 because higher order poles and zeros are neglected when using the opamp transfer function specified in Problem 5.2.
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The LTspice schematic includes a ‘.meas’ directive to find the phase margin PM. The phase margin is PM=180° − (−L(j ft)) =180° + (L(j ft) = (−L(j ft)) where L(j f) is the loop gain and ft
is the frequency where |L(j f)| has dropped to a value of 1. Thus, the phase of -v(Vr) is equal to the phase margin when the magnitude of v(Vr) is equal to 1. From the error log file, we find
‘pm: -v(vr)=(-0.000110864dB,70.0749°) at 1.94705e+007’, i.e., a phase margin of 70° and a unity gain frequency of 19.47 MHz for the loop gain. These results closely match the results from the plot.
Problem 5.3
Design a bandpass biquad filter block by interchanging L1 and R1 from the lowpass biquad shown in Table 5.3.
Simulate a bandpass filter using the filter block with fo=20 MHz andQ=4. Find the passband gain and the 3-dB bandwidth.
Solution:
Table 5.3 is shown in the solution for Problem 5.2. By interchangingL1andR1in the schematic for the low-pass biquad, we obtain the following LTspice schematic for a bandpass biquad. Remember to save the file as ‘BP2.asc’.
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The transfer function for this circuit is
T(j f) = YR
YR+YC+YL
InsertingYR=1/R,YC= jωC= j(2πf)CandYL=1/(jωL) =1/(j(2πf)L), we find T(j f) = 1/R
1/R+j(2πf)C+1/(j(2πf)L) = j(2πf)L/R
j(2πf)L/R+CL(j2πf)2+1 Inserting the values ofR,LandCfrom the schematic, we find
T(j f) = j f/(foQ) 1+j f/(foQ) + (j f/fo)2 which is a second-order bandpass function.
When using the command ‘Hierarchy→Open this Sheet’s Symbol’, a new window opens with a message from LTspice: ‘Couldn’t find this sheet’s symbol. Shall I try to automatically generate one?’ Answering
‘Yes’ results in a new sheet being opened with a symbol which is just a box with the output terminal on the right side and the input terminal on the left side. By using the ‘Edit’ and ‘Draw’ commands in the symbol editor, the symbol may be modified to look like shown in the following figure.
When you click ‘File→Save’, the symbol is saved in the same folder as the subcircuit schematic file.
You may select to save the subcircuit schematic and symbol in another folder by using ‘File→ Save As’. Remember to specify a path to this folder using the command ‘Tools→Control Panel→Sym. &
Lib. Search Paths’.
For simulating the bandpass filter, we draw the following LTspice schematic. For specifying the parame- ters foandQ, we use a right-click on the subcircuit symbol. This opens a window where you can specify parameters for the subcircuit in the line ‘PARAMS:’. Also tick the box next to the specification line in order to make the parameters visible on the schematic.
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The plot from the ac simulation is shown below. We find a passband gain of 0 dB and a bandwidth of 22.66 MHz−17.66 MHz=5.00 MHz.
The passband gain and the bandwidth can also be found from the ‘.meas’ directives shown in the LT- spice schematic. The error log file reports ‘gain: MAX(mag(v(vo)))=(-2.7648e-010dB,0°) FROM 1e+007 TO 4e+007’, i.e., a passband gain of 0 dB, and ‘bw=5.00005e+006 FROM 1.76556e+007 TO 2.26557e+007’, i.e., a 3-dB bandwidth of 5 MHz. Theoretically, the bandwidth is fo/Qwhich is also equal to 5 MHz.
Problem 5.4
Design a highpass biquad filter block by interchanging L1 andC1 from the lowpass biquad shown in Table 5.3.
Simulate a highpass filter using the filter block with fo=20 MHz andQ=4. Find the passband gain, the frequency where the gain has its maximum magnitude and the magnitude of the peak in the frequency response.
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Solution:
Table 5.3 is shown in the solution for Problem 5.2. By interchangingL1andC1in the schematic for the low-pass biquad, we obtain the LTspice schematic for a highpass biquad shown below. Remember to save the file as ‘HP2.asc’.
The transfer function for this circuit is
T(j f) = YC
YR+YC+YL
InsertingYR=1/R,YC= jωC= j(2πf)CandYL=1/(jωL) =1/(j(2πf)L), we find T(j f) = j(2πf)C
1/R+j(2πf)C+1/(j(2πf)L) = (j2πf)2CL
j(2πf)L/R+CL(j2πf)2+1 Inserting the values ofR,LandCfrom the schematic, we find
T(j f) = (j f/fo)2
1+j f/(foQ) + (j f/fo)2 which is a second-order highpass function.
When using the command ‘Hierarchy→Open this Sheet’s Symbol’, a new window opens with a message from LTspice: ‘Couldn’t find this sheet’s symbol. Shall I try to automatically generate one?’ Answering
‘Yes’ results in a new sheet being opened with a symbol which is just a box with the output terminal on the right side and the input terminal on the left side. By using the ‘Edit’ and ‘Draw’ commands in the symbol editor, the symbol may be modified to look like shown in the following figure.
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When you click ‘File→Save’, the symbol is saved in the same folder as the subcircuit schematic file.
You may select to save the subcircuit schematic and symbol in another folder by using ‘File→ Save As’. Remember to specify a path to this folder using the command ‘Tools→Control Panel→Sym. &
Lib. Search Paths’.
For simulating the highpass filter, we draw the LTspice schematic shown below. For specifying the parameters foandQ, we use a right-click on the subcircuit symbol. This opens a window where you can specify parameters for the subcircuit in the line ‘PARAMS:’. Also tick the box next to the specification line in order to make the parameters visible on the schematic.
The plot from the ac simulation is shown below. We find a gain of 0 dB and a peak of 12.1 dB at a frequency of 20.3 Mhz. It may be noted that the exact location of the peak is not so easy to determine from the plot and a large number of points per octave is needed.
The peak and the frequency of the peak can also be found from the ‘.meas’ directives shown in the schematic. The error log file reports ‘peak: MAX(mag(v(vo)))=(12.1096dB,0°) FROM TO 4e+008’
and ‘fmax: mag(v(vo))=peak AT 2.03224e+007’. We notice that these results provide a very good match to the results found from the plot.
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Problem 5.5
The amplifier shown in Fig. 5.22 (top) may be modeled as a biquad bandpass function with a very low value ofQ. Use the specification of the lower−3 dB frequency (20 Hz) and the upper−3 dB frequency (20 kHz) to find foandQand simulate the amplifier using the bandpass biquad from Problem 5.3 and a voltage-controlled voltage source to provide the midband gain of 20 dB. Compare the simulated response to the response shown in Fig. 5.22.
For convenience, Fig. 5.22 is shown below.
Figure 5.22:Audio amplifer (schematic and frequency response).
Solution:
For a second-order bandpass filter, the resonance frequency fois given by (Sedra & Smith 2016, p. 1099) fo=
fp1fp2=632.46 Hz where fp1=20 Hz is the lower−3 dB frequency and fp2=20 kHz is the upper −3 dB frequency. The bandwidth BW is given by BW= fp2−fp1= fo/Q⇒Q= fo/BW= 632.46 Hz/(20 kHz−20 Hz) =0.03165.
Inserting these values as parameters for the filter block BP2.asc from Problem 5.3 results in the following LTspice schematic. Also a voltage-controlled voltage source is included to provide the midband gain of 20 dB.
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The plot from a ‘.ac’ simulation is shown below. It is identical to the plot in Fig. 5.22.
Problem 5.6
Design subcircuits and symbols for a two-input NAND gate, a two-input NOR gate and a three-input NOR gate similar to the logic gate and inverter designs shown in Example 5.4. Also design a subcircuit and a symbol for a transmission gate (T-gate) requiring both an inverted control input C and a noninverted control input C. The T-gate should be on when the control input C is high. Scale the PMOS transistors relative to the NMOS transistors to compensate for the difference in electron mobility and hole mobility, assumingµn=3µp. Use the BSIM3 transistor models NMOS-BSIM and PMOS-BSIM from Fig. 3.10 with a channel length of Lmin for all transistors and a minimum channel width of 3Lmin for NMOS transistors and 9Lminfor PMOS transistors.
What are the transistor channel widths used for the gates?
Figure 3.10 may be found in the Introduction of this book.
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Solution:
The following figures show the schematics and symbols for each of the gates NOR2, NOR3, NAND2 and T-gate. In order to compensate for the difference in hole mobility and electron mobility, the channel widths have been selected as follows:
NOR2:Wn=3Lmin,Wp=18Lmin. NOR3:Wn=3Lmin,Wp=27Lmin. NAND2:Wn=6Lmin,Wp=9Lmin. T-gate:Wn=3Lmin,Wp=9Lmin.
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The symbols for the gates are created from the schematics using the command ‘Hierarchy → Open this Sheet’s Symbol’ which opens a window with a message from LTspice: ‘Couldn’t find this sheet’s symbol. Shall I try to automatically generate one?’ Answering ‘Yes’ results in a new sheet being opened with a symbol which is just a box with the output terminal and bidirectional terminals on the right side and the input terminals on the left side. By using the ‘Edit’ and ‘Draw’ commands in the symbol editor, the symbol may be modified to look like the symbols shown above.
Hint: You may find that the drawing of the arcs, especially for the NOR gates is not so easy. However, the
‘*.asy’ files are simple text files, so if you have created some good-looking arcs for one of the symbols, you may open the text files with a text editor like Notepad and copy the specification of the arcs from one file to another. Shown in the following is the text file ‘NOR2.asy’. Evidently, the lines beginning with
‘ARC’ specify the three arcs in the symbol and they may be copied to the symbol for NOR3 to ensure the same symbol outline for NOR3 as for NOR2.
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Version 4
SymbolType BLOCK
CIRCLE Normal 32 6 20 -6
ARC Normal -125 -48 -29 48 -38 28 -38 -28 ARC Normal -121 -132 39 28 -38 28 28 6 ARC Normal -121 132 39 -28 28 -6 -38 -28 WINDOW 0 8 -40 Bottom 2
PIN -32 -16 NONE 8 PINATTR PinName X1 PINATTR SpiceOrder 1 PIN -32 16 NONE 8 PINATTR PinName X2 PINATTR SpiceOrder 2 PIN 32 0 NONE 8 PINATTR PinName Y PINATTR SpiceOrder 3 Problem 5.7
Use the inverter from Fig. 5.25 to design a ring oscillator as shown above. Use the BSIM3 transistor models from Fig. 3.10 with a channel length of Lmin=0.35 µm and a supply voltage of 3 V. With
‘Fanout=1’ andCF =0.2 pF, find the frequency of oscillation. Also find the inverter delay for an inverter loaded with an identical inverter.
Repeat for ‘Fanout=5’ for all of the inverters.
Hint: To start the oscillation, inject a short current pulse in the output node.
For convenience, Fig. 5.25 is shown in Problem 5.1 and Fig. 3.10 may be found in the Introduction of this book.
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Solution:
The figure below shows the oscillator schematic in LTspice. For finding the frequency of oscillation, we run a ‘.tran’ simulation. The resulting plot of the output voltage is shown below. Using the cursors, the time for 4 periods of oscillation, 4T, is found, and the frequency is found as fosc=1/T =4/(4T) = 4/(14.47 ns−8.11 ns) =629 MHz.
For finding the inverter delay, we plot the voltagesvim1andvim3defined in the schematic. The delay between rising edges ofvim1andvim3corresponds to two inverter delays. The figure below shows the simulation plot zoomed in on a short interval around 7.4 ns. Using the cursors, we find the delay from vim1tovim3to be 143 ps, so the inverter delay is 72 ps.
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Alternatively, we may find the results from the ‘.meas’ directives shown in the schematic.
The first directive finds the time between two consecutive rising edges of vim1, the 10th edge and the 11th edge. The error log file reports ‘period=1.58975e-09 FROM 1.52724e-08 TO 1.68622e-08’, corresponding to a frequency of 629 MHz.
The second directive finds the time between the 10th rising edge of vim1 and the 10th rising edge of vim3, corresponding to two inverter delays. The error log file reports ‘2tdelay=1.43925e-10 FROM 1.52724e-08 TO 1.54163e-08’, corresponding to a delay of 72 ps. This is an average delay. There may be a difference between the delaytphlfrom a rising input edge to a falling output edge and the delay tplhfrom a falling input edge to a rising output edge.
The third directive finds the delaytphl from a rising input to a falling output. The error log file reports
‘tphl=7.98608e-11 FROM 1.52724e-08 TO 1.53523e-08’, i.e., a delay of 80 ps.
The fourth directive finds the delaytplh from a falling input to a rising output. The error log file reports
‘tplh=6.40637e-11 FROM 1.53523e-08 TO 1.54163e-08’, i.e., a delay of 64 ps. We notice that the average delay is 72 ps as also found from the second ‘.meas’ directive.
Repeating the simulation with a fanout of 5 for the inverters, we find an oscillation frequency of fosc= 1074 MHz and an average delay oftd=64 ps from the simulation plots below:
From the error log file, we find the following results from the ‘.meas’ directives:
Error log file, .op simulation
This corresponds to an oscillation frequency of 1076 MHz, an average delay 64 ps, a delay from rising input to falling output of 69 ps and a delay from falling input to rising output of 58 ps, all results matching the results from the simulation plot very well.
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Problem 5.8
The figure above shows the symbol and logic diagram for a positive-edge-triggered D-type flip-flop with active high set and reset and complementary outputs. Use the subcircuits from Problem 5.6 and the in- verter from Fig. 5.25 with ‘Fanout=1’ to design an LTspice symbol and subcircuit for the flip-flop.
Use the flip-flop to design a divide-by-two circuit and connect a clock signal with a frequency of 100 MHz to the clock input. Use the BSIM3 transistor models from Fig. 3.10 with Lmin=0.35 µm and a supply voltage ofVDD=3 V.
Find the propagation delay from the rising edge of the clock input to the Q-output both for Q rising (tplh) and for Q falling (tphl) when the Q-output is loaded by 3 inputs from two-input NAND gates.
Also find the rise timetrand the fall timetf for Q changing between 10% and 90% ofVDD.
For convenience, Fig. 5.25 is shown in Problem 5.1 and Fig. 3.10 may be found in the Introduction of this book.
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Solution:
Shown below is the D-type flip-flop drawn as an LTspice subcircuit and the corresponding LTspice symbol.
The following LTspice schematic shows a divide-by-two counter stage where the Q output is loaded by 3 inputs from two-input NAND gates. The clock input is specified using a pulse input with a frequency of 100 MHz, a duty cycle of 50% and very short rise time and fall time.
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