Problem 3.1
W=10 µm,L=1 µm,
Kp=55 µA/V2,Vto=−0.71 V,λ =0.16 V−1, γ=0.75√
V,|2ΦF|=0.7 V.
For the PMOS transistor shown above, simulate and plot the input characteristics ID versusVSG and
∂iD/∂vSGforVSD=0, 0.5, 1.0, 1.5, 2.0, 2.5 and 3.0 V. Use the model parameters and transistor dimen- sions shown above. Find the bias currentIDand the small-signal parametersgm,gmbandgdsfor the bias point ofVSG=1.5 V andVSD=2.0 V.
Solution:
The figure below shows the schematic for simulating the input characteristics. Also shown are the resul- ting plots of ID versusVSG and∂iD/∂vSG (or gm) forVSD=0 V (green curves), 0.5 V (blue curves), 1.0 V (red curves), 1.5 V (cyan curves), 2.0 V (purple curves), 2.5 V (grey curves) and 3.0 V (dark green curves). You may notice that when the transistor is in the triode region (|VDS|<|VGS| − |Vt|), gmis independent ofVSG, see Eq. (3.11) in ‘CMOS Integrated Circuit Simulation with LTspice’.
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For finding the bias current and the small-signal parameters for a bias point ofVSG=1.5 V andVSD= 2.0 V, we run a ‘.op’ simulation (shown as a comment in the LTspice schematic). The bias values and the small-signal parameters are given in the error log file (‘Ctrl-L’) from this simulation, see below where the requested parameters are underlined.
Notice that in LTspice, the drain current is defined positive into the transistor, hence the negative value ofIdin the error log file.
LTspice Error Log
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Problem 3.2
For an NMOS transistor with the transistor model shown above (BSIM3 0.35 µm model, Fig. 3.10) and channel widthW =10 µm, simulate and plotIDversus the channel lengthLin the interval 1 µm<L<
10 µm for a bias point ofVGS=1.5 V,VDS=2.0 V andVSB=0 V. Find the bias current ID and the small-signal parametersgm,gmbandgdsforL=1 µm and forL=5 µm in the bias point.
Hint: DefineLas a parameter and stepLfrom 1 µm to 10 µm.
Figure 3.10 may be found in the Introduction of this book.
Solution:
The following figure shows the schematic for simulating the drain current. The channel length L is defined as a parameter which is stepped from 1 µm to 10 µm. The transistor model is included in a separate model file, ‘BSIM3_035.lib’. The drain current is found from a ‘.op’ simulation.
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For finding the bias current ID and the small-signal parametersgm, gmb andgds forL=1 µm and for L=5 µm in the bias point ofVGS=1.5 V,VDS=2.0 V andVSB=0 V, we specify the value ofLusing a ‘.param’ directive (shown as comments in the LTspice schematic) while the ‘.step param’ directive is changed into a comment.
The bias point information is given in the error log file from a ‘.op’ simulation. The error log files for L=1 µm andL=5 µm are shown below with an underlining of the requested parameters. We notice that with the BSIM transistor model, neither the bias current, nor the transconductances (gmandgmb) scale by a factor of 5 as predicted by the Shichman-Hodges model.
LTspice Error Log,L=1 µm LTspice Error Log,L=5 µm
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Problem 3.3
For a PMOS transistor with the transistor model shown above (BSIM3 0.35 µm model, Fig. 3.10) and channel widthW =10 µm and channel lengthL=1 µm, simulate and plot the input characteristicsID
versusVSGforVSD=0, 0.5, 1.0, 1.5, 2.0, 2.5 and 3.0 V. AssumeVBS=0 V. Also simulate and plot the output characteristicsIDversusVSDforVSG=0, 0.5, 1.0, 1.5, 2.0, 2.5 and 3.0 V. Use the cursors to find IDand∂iD/∂vSDforVSG=1.5 V,VBS=0 V andVSD=2.0 V.
Figure 3.10 may be found in the Introduction of this book.
Solution:
The following figure shows the schematic for simulating the input characteristics. Also shown is the resulting plot ofIDversusVSGforVSD=0 V (green curve), 0.5 V (blue curve), 1.0 V (red curve), 1.5 V (cyan curve), 2.0 V (purple curve), 2.5 V (grey curve) and 3.0 V (dark green curve). Because of the difference in sign conventions between textbooks and LTspice, the following plot shows-Id(M1)which is equal toIDusing the normal textbook convention.
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For simulating the output characteristics, we modify the simulation directive to have ‘V2’ as the first source to sweep and ‘V1’ as the second source to sweep. The following figure shows the output charac- teristics, i.e., a plot ofIDversusVSDforVSG=0 V (green curve, not visible because of the blue curve), 0.5 V (blue curve), 1.0 V (red curve), 1.5 V (cyan curve), 2.0 V (purple curve), 2.5 V (grey curve) and 3.0 V (dark green curve).
For finding IDforVSG=1.5 V,VBS =0 V andVSD=2.0 V, the output characteristics above are used with a cursor placed on the cyan curve as shown. The cursor is shifted from one curve to another by the up/down arrow keys. We findID=160 µA.
For finding∂iD/∂vSDforVSG=1.5 V,VBS=0 V andVSD=2.0 V, the derivative ofIDis plotted as shown in the following figure. It may be a good idea to zoom in on the relevant part of the characteristics as also shown in the figure. We find∂iD/∂vSD=7.32 µA/V.
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We may verify the results by running a ‘.op’ simulation withVSG=1.5 V,VBS=0 V andVSD=2.0 V (the values shown in the LTspice schematic). From the error log file, we find the results shown below where the drain current and the output conductance are underlined.
LTspice Error Log
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Problem 3.4
For a PMOS transistor with the transistor model shown above (BSIM3 0.35 µm model, Fig. 3.10) and channel widthW =10 µm and channel lengthL=1 µm, find the bias currentIDand the small-signal parameters gm, gmb and gds in a bias point ofVSG =1.5 V,VBS =0 V andVSD=2.0 V. From these small-signal parameters and the bias current, estimate parameters for a Shichman-Hodges model for the transistor. Assume|2ΦF|=0.7 V.
Simulate and plot the input characteristics (ID versusVSG) and output characteristics (ID versusVSD) using both the BSIM model and the Shichman-Hodges model with the parameters estimated from the simulation of small-signal parameters in the bias point.
Figure 3.10 may be found in the Introduction of this book.
Solution:
The following figure shows the schematic for simulating the small-signal parameters and the resulting error log file with the relevant parameters underlined.
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LTspice Error Log
From the small-signal parameters, the following Shichman-Hodges model parameters are calculated.
Beware of the signs. For a PMOS transistor, the easiest solution is to use absolute values in Eqs. (3.12) to (3.15) in ‘CMOS Integrated Circuit Simulation with LTspice’. Remember that the threshold voltage is negative for a PMOS transistor.
λ = gds
|ID| −gds|VDS|=0.05 V−1 Vto = −
|VGS| −2|ID| gm
=−0.556 V Kp =
gm
|ID|
2
|ID| −gds|VDS| 2(W/L)
=32.6 µA/V2
|2ΦF| = 0.7 V γ = 2
|2ΦF| gmb
gm =1.67 gmb
gm =0.37√ V
For simulating the input characteristics and the output characteristics for both the BSIM3 transistor model and the Shichman-Hodges transistor model, the schematic shown below is used. The ‘.dc’ command spe- cification shown gives the output characteristics. For the input characteristics, use ‘V1’ as the first source and ‘V2’ as the second source.
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The simulations result in the characteristics shown below with the green curves for the BSIM3 model and the blue curves for the Shichman-Hodges model.
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Problem 3.5
For an NMOS transistor with the transistor model shown above (BSIM3 0.35 µm model, Fig. 3.10), a channel widthW =10 µm and channel length L=1 µm, assume a bias point specified byVGS=VDS, VSB=0 V andID=140 µA. Findgm,gmbandgds from a ‘.op’ simulation and estimate parametersKp, Vto,λ andγfor a Shichman-Hodges model for the transistor. Assume|2ΦF|=0.7 V.
Figure 3.10 may be found in the Introduction of this book.
Solution:
The following figure shows the schematic for simulating the small-signal parameters and the resulting error log file with the relevant parameters underlined.
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LTspice Error Log
From the small-signal parameters, the following Shichman-Hodges model parameters are calculated using Eqs. (3.12) to (3.15) in ‘CMOS Integrated Circuit Simulation with LTspice’.
λ = gds
ID−gdsVDS =0.045 V−1 Vto = VGS−2ID
gm =0.520 V Kp =
gm
ID
2
ID−gdsVDS
2(W/L)
=117 µA/V2
|2ΦF| = 0.7 V γ = 2
|2ΦF|gmb
gm =1.67 gmb
gm =0.48√ V Problem 3.6
An NMOS transistor is assumed to have the following Shichman-Hodges parameters:Kp=190 µA/V2, Vto=0.57 V,λ =0.16 V−1,γ=0.5√
V and|2ΦF|=0.7 V. The channel length isL=1 µm. Simulate and plot gm and gds versus the drain current ID forW =10 µm,W =30 µm andW =50 µm, and 0<ID<10 mA. Assume a drain-source voltage ofVDS=1.2 V.
From the plots ofgm andgds, find the maximum drain current for which the transistor is in the active region for each of the three values of channel width.
Solution:
For simulating the small-signal parametersgmandgds, we use a circuit similar to the circuit shown in Fig. 3.40 in ‘CMOS Integrated Circuit Simulation with LTspice’. For convenience, this figure is shown in the following.
For the simulations for findinggmandgdsversusID, the following LTspice schematic is used. Two ‘.step’
directives are inserted, one forIDand one forW. The ‘.step’ directive forIDis inserted first in order to defineIDas the first parameter to step, i.e., defining the x-axis in the output plot from the simulation.
The step size forIDhas been chosen to be small, 0.01 mA, in order to get a smooth simulation plot all the way down to 0 mA.
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Figure 3.40:NMOS current mirror with voltage buffer for the drain voltage for simulating bothgdsandgm.
From the ‘.tf’ simulation, the transconductancegmis found as ‘1/i1#Input_impedance’ and the output conductancegdsis found as ‘1/output_impedance_at_V(vd2)’, both of which are shown below. The green curves are forW=10 µm, the blue curves are forW=30 µm, and the red curves are forW=50 µm.
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Clearly, there is a kink in each of the curves, indicating the limit between the active region (small values of drain current) and the triode region (large values of drain current). From the kinks, we find the following maximum values of drain current for which the transistor is in the active region:
W=10 µm:IDmax=1.65 mA.
W=30 µm:IDmax=4.95 mA.
W=50 µm:IDmax=8.23 mA.
In the active region,gmis found from gm=
2µnCox
W
L
ID(1+λVDS)
showing a square root dependency onID, see Eq. (3.8) in ‘CMOS Integrated Circuit Simulation with LTspice’.
In the triode region,gmis found from
gm=µnCox
W
L
VDS(1+λVDS)
showing that gm does not depend on ID, see Eq. (3.11) in ‘CMOS Integrated Circuit Simulation with LTspice’.
Forgds, we note that in the active region,
gds= λID
1+λVDS
showing thatgdsis independent ofW and linearly increasing withID, see Eq. (3.9) in ‘CMOS Integrated Circuit Simulation with LTspice’.
In the triode region, an approximate expression forgds(neglectingλ) is gds= ∂iD
∂vDS =µnCox
W
L
(VGS−Vt−VDS) Using
ID=µnCox
W
L
[(VGS−Vt)VDS−VDS2 /2]⇒VGS−Vt= ID/VDS
µnCox(W/L)+VDS/2 we find
gds= ID
VDS−1 2µnCox
W
L
VDS
showing thatgdsincreases linearly withIDand decreases linearly withW as also found from the simula- tion.
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Problem 3.7
An NMOS transistor is assumed to have the following Shichman-Hodges parameters:Kp=190 µA/V2, Vto=0.57 V, λ =0.16 V−1,γ=0.5√
V and|2ΦF|=0.7 V. The channel length isL=1 µm and the channel width isW =20 µm. Simulate and plot gm/gds versus the drain currentID for 1 µA<ID<
100 µA. Assume a drain-source voltage ofVDS=1.5 V.
Also plotgm/gdsversus 1/√
ID. Findgm/gdsforID=1 µA andID=100 µA.
Solution:
For simulatinggmandgds, we use the circuit shown in Fig. 3.40 in ‘CMOS Integrated Circuit Simulation with LTspice’ (also shown in the solution for Problem 3.6 in this book).
Shown below is the LTspice schematic for Problem 3.7 and withgmfound as ‘1/i1#Input_impedance’
and gds found as ‘1/output_impedance_at_V(vd2)’, we can plot gm/gds (the intrinsic gain) as
‘output_impedance_at_V(vd2)/i1#Input_impedance’.
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From the plot, we findgm/gds=751 forID=1 µA andgm/gds=75.1 forID=100 µA.
In order to showgm/gds versus 1/√
ID, we move the cursor to the horizontal axis and right-click. In the window for ‘Quantity plotted’, we enter ‘1/sqrt(Id)’. The resulting plot is shown below. It is clearly seen that the intrinsic transistor gaingm/gdsis inversely proportional to√
IDwhen using the Shichman- Hodges transistor model.
Problem 3.8
W1=W2=20 µm,L1=L2=1 µm, AD1=AD2=20×10−12m2 PD1=PD2=22 µm.
For the current mirror shown above, use a ‘.ac’ simulation to find the input resistance and the input capacitance. Assume that the input impedance can be approximated by a parallel connection of a capac- itance and a resistance so that Eqs. (2.16) and (2.17) can be used. Assume a dc value of 100 µA for the input current and use the transistor dimensions shown above. Also, use the BSIM3 transistor model from Problem 3.5 (BSIM3 0.35 µm model, Fig. 3.10).
Find the input resistance and input capacitance for two different values of the load resistor: RL=0Ω andRL=10 kΩ.
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Figure 3.10 may be found in the Introduction of this book.
Solution:
The LTspice schematic for simulating the current mirror is shown below. Notice the ‘.step’ directive for RL. As LTspice does not accept a value of 0 for a resistor,RLis stepped between the values 0.01Ωand 10 kΩ. For finding the input resistance and input capacitance, we plot ‘Abs(V(vg))**2/Re(V(vg))’
and ‘-Im(V(vg))/(Abs(V(vg))**2*2*pi*frequency)’, respectively, compare Eqs. (2.22) and (2.23) in ‘CMOS Integrated Circuit Simulation with LTspice’.
The plots are shown below. From the plots, we findRin=1.206 kΩ, independent ofRL,Cin=0.146 pF forRL=0ΩandCin=0.190 pF forRL=10 kΩ.
The increase in input capacitance forRL=10 kΩis caused by the gain from gate to drain of M2, causing a Miller effect on the gate-drain capacitance of M2, compare for instance the example given in Fig. 2.27 in ‘CMOS Integrated Circuit Simulation with LTspice’.
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