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The simulation is run directly from the netlist file in LTspice using the ‘Simulate→Run’ command (or
‘Ctrl-R’), and in the plot window which opens, the traces to plot are selected using ‘Plot Setting→Add trace’ (or ‘Ctrl-A’). For finding the common-mode output voltage, we plot the output voltagesV(4)and V(5)and read the value for a differential input voltagevidof 0 V. We notice thatV(4)=V(5)for an input voltage of 0 V. For finding the differential gain, we plot the derivative of the differential output voltage, i.e.,d(V(4)-V(5))and find the value for an input voltage of 0 V. From the plots below, we find a common-mode output voltage of 1.75 V and a differential gain of 9.12 V/V.
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Problem 7.2
Use the netlist from Problem 7.1 to design a subcircuit and a subcircuit symbol for the differential pair.
Use the BSIM3 transistor model from Fig. 3.10. Design the subcircuit to have separate terminals for the supply voltage and the bias current. Insert the differential pair in a test bench as shown in the figure below and find the low-frequency differential gain and the−3 dB frequency for the differential gain. Use VDD=3 V,IB=250 µA,VCM=1.5 V andCL=3 pF.
Figure 3.10 may be found in the Introduction of this book.
Solution:
The netlist from Problem 7.1 is modified by including a ‘.subckt’ directive and a ‘.ends’ directive as shown below. By placing the cursor in the ‘.subckt’ line and right-clicking, a symbol is generated, and using the graphic symbol editor, this may be modified into the symbol shown below. To ensure portability of the symbol, you can save the symbol (difpair.asy) and the netlist file (difpair.net) in the same folder as the schematic of your testbench. Also use the command ‘Edit → Attributes→ Edit Attributes’ in the symbol editor to specify just ‘difpair’ as the ‘ModelFile’ rather than the full path name to the file
‘difpair.net’.
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The figure below shows a testbench corresponding to Problem 7.2 and a plot of the differential output voltage. From the plot, we find a low-frequency differential gain of 19.2 dB and a−3 dB frequency of 2.84 MHz.
The low-frequency differential gain and the−3 dB frequency for the differential gain may also be found using the ‘.meas’ directives shown in the schematic. From the error log file, we findAd=19.2 dB and BW=2.84 MHz, exactly matching the results from the plot of the output voltage.
Problem 7.3
Redefine the subcircuit from Problem 7.2 to have the transistor channel width as a parameter which can be defined at top level. Use the testbench from Problem 7.2 to find the low frequency gain and the
−3 dB frequency as a function of the channel width for 5 µm≤W ≤30 µm. What is the value of the low frequency gain and the−3 dB frequency forW=5 µm and forW=30 µm?
Solution:
The netlist from Problem 7.2 is modified by specifying the channel width as a parameter. Also, the subcircuit is renamed to ‘difpairw’ with a corresponding symbol as shown in the following figure.
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The testbench from Problem 7.2 is modified by replacing the subcircuit ‘difpair’ with ‘difpairw’ and including a ‘.step’ directive to sweep the channel width. The resulting ‘.ac’ simulation has many traces, see below.
In order to find the low-frequency gain and the−3 dB frequency versus channel width, we open the error log file and right-click to ‘Plot .step’ed .meas data’. Using the command ‘Plot Settings→Add Trace’, you can select the traces to plot. In the following figure, separate plot panes are used for the gainAdand the−3 dB frequency BW. From the plot, we find a gain of 4.15 V/V forW =5 µm and 12.9 V/V for W=30 µm and a−3 dB frequency of 2.77 MHz forW=5 µm and 2.89 MHz forW =30 µm.
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Problem 7.4
Use FinFET transistors to design an inverting amplifier similar to the amplifier shown in Fig. 7.26 but with the SGNMOS transistor replaced by a series connection of three SGNOS transistors with a single fin and the SGPMOS transistor replaced by a series connection of two SGPMOS transistors with a single fin, i.e., F=1 for all transistors. Simulate the dc transfer characteristics and the gain. Find the input bias voltageVIN resulting in the maximum absolute value of the small-signal gainvout/vin and find the maximum absolute value of the gain. Also find the small-signal output resistance of the amplifier for the input bias voltage resulting in the maximum absolute value of the gain.
Solution:
Using the FinFET transistor models and symbols from Example 7.3, we may draw the following LTspice schematic.
The FinFet symbols and models may be downloaded from web page of ‘CMOS Integrated Circuit Sim- ulation with LTspice’, https://bookboon.com/en/cmos-integrated-circuit-simulation-with-ltspice-ebook.
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The ‘.dc’ simulation specified in the schematic results in the following plot ofvOUT and the small-signal gainvout/vin. The ‘.dc’ simulation may be run with a value of 0 forV1. The gain is found asd(v(VOUT)).
From the plot of the gain, we find a maximum gain (absolute value) of 4.76 V/V for an input voltage of 0.445 V.
Alternatively, the maximum gain and the corresponding input bias voltage may be found using the
‘.meas’ directives shown in the schematic.
From the error log file, we find ‘maxgain: MAX(abs(d(v(vout))))=4.75705 FROM 0 TO 10’ and
‘vin: abs(d(v(vout)))=maxgain AT 0.4451’, matching the values found from the plot very well.
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