VLSI 90nm foils 0604

(1)

Delaying Forever:

Uniaxial Strained Silicon Transistors

in a 90nm CMOS Technology

K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffman, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson#,

M. Bohr

Logic Technology Development Intel Corporation

(2)

Key Messages

• Biaxial vs. Uniaxial strain

– Electron mobility gain similar for both stress types

– Hole mobility gain superior for uniaxial strain

• Epitaxial S/D transistor structure

– Large uniaxial strain

– Improved R_EXT so full mobility benefit is realized

(3)

3

Outline

• Introduction

• Why Uniaxial Strain?

• Transistor Results

• Performance & Power

(4)

Transistor Scaling: The Mobility Challenge

• Mobility degrades with transistor scaling

– Universal mobility model

– Ionized impurity scattering

10

on Mobilit

y

(5)

5

on Mobilit

y

Source: Intel Technology

Strain Enhanced Mobility

• Strain can be used to enhance mobility

(6)

Biaxial Tensile Strain

Biaxial tensile strain studied extensively last 10 years

– Large electron mobility gain, but...

Two key problems:

1. Integration difficulties – Dislocations

– Ge Up-diffusion

– Fast diffusion of extensions

– Cost

2. Poor hole mobility gain

n+

Relaxed Si_1-xGe_x

Si Substrate Strained Si

STI

Gate

Graded Si_1-yGe_y

(7)

7

Outline

(8)

Biaxial vs. Uniaxial Strain: Electrons

• Electron mobility enhancement similar

– Both cases result from splitting of 6-fold degenerate valleys

– Only valley shifting responsible for mobility gain

– Negligible band curvature change in either case

<100> <010>

<001> _∆

2

(9)

9

Biaxial vs. Uniaxial Strain: Holes

• Uniaxial stress more effective than biaxial for hole mobility improvement

– Simple calculations using peizoresistance coefficients

[C.S. Smith, Phys. Rev., 1954]

Longitudinal compressive

Compressive stress <001> (Biaxial in plane tension)

Tranverse tensile

<110> channel orientation (001 surface)

(10)

Biaxial vs. Uniaxial Strain: Holes

• Biaxial strain: hole mobility gain lost at high E_EFF

– Mobility gain due to lower scattering: separation of LH & HH bands Î Not due to reduction in hole effective mass

– At high E_EFF LH – HH separation reduced due to quantization Î Hole mobility gain is lost

Strain Quantization LH

Universal Hole Mobility

Biaxial Strain Rim

et al 1995

(11)

11

Biaxial vs. Uniaxial Strain: Holes

• Uniaxial strain: high hole mobility at high E_EFF

– Mobility gain from effective mass reduction Î Change in band warping [Giles, VLSI04] – Band separation not reduced at high E_EFF

Î High out of plane effective mass for light holes

40

Universal Hole Mobility

Uniaxial Strain Rim

et al 1995

(12)

Outline

(13)

13

Uniaxial Strain Structures

• Two uniaxial strain structures incorporated in our 90nm CMOS technology

– Epitaxial S/D Transistor for PMOS

– Tensile capping layer for NMOS

High Stress Film

(14)

Transistor Results: PMOS

• Astounding PMOS drive current of 0.72 mA/µm!

– at 1.2V and I_OFF= 40nA/µm

– 30% I_DSAT gain from strain enhanced mobility

0.1

(15)

15

Transistor Results: Channel Strain

• Simulations show Epitaxial S/D transistor has uniaxial compressive channel strain [Giles VLSI04]

– Predicts 55% hole mobility gain

• TEM electron diffraction

measurements confirm 0.6%

lattice displacement SiGe

Channel

(16)

Transistor Results: I

_DLIN

& Strain

• I_DLIN gain vs. L_GATE correlated to stress from 2.0µm to 0.1µm

• Both R_EXT and strain contribute to gain for < 0.1µm

• Net I_DLIN gain of 55% vs. simulated mobility gain of 55%

– Full mobility gain seen in I_DLIN; Epi S/D transistor also improves R_EXT

0

Improved R_EXT

(17)

17

Transistor Results: Pattern Dependence

• PMOS I_DSAT for min. poly pitch vs. wider pitch

– Initial results showed a large difference

– Minimized with process optimization

0

Process 1 Process 2 Process 3

(18)

Transistor Results: NMOS

• Record NMOS drive current of 1.26 mA/um

– 10% I_DSAT gain from tensile strain layer

1 10 100 1000

0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

IDSAT (mA/um)

IO

40nA/um

(19)

19

Transistor Results: CMOS

• Tensile capping layer improves NMOS IDSAT with no significant PMOS IDSAT loss

0

(20)

Outline

(21)

21

Performance

• Strained silicon results in fast ring oscillators

– Delay per stage of 4.6pS for low VT devices

4 5 6 7

10 100 1000 10000

IOFF-N + IOFF-P (nA/um)

(22)

Power: Leakage Reduction

• Strained silicon: high performance, low power

– Performance: 30% I_DSAT gain at fixed I_OFF

(23)

23

Power: SRAM VCCmin

• Strain silicon also improves SRAM VCCmin

– Important for long battery life in mobile applications

– Strain enhanced PMOS balances V_T mismatch in NMOS

– 50Mb SRAM with 1.0µm2 _{cell functional down to 0.65V}

VT mismatch

induced leakage

Strain enhanced

PMOS

Cycle Time (ns)

VD

D

(V)

0.6 3.0

(24)

Summary

• Uniaxial strain has significant advantages over biaxial strain for hole mobility enhancement

• Epitaxial S/D transistor structure provides

– Large uniaxial channel strain

– >50% hole mobility gain and lower R_EXT

– I_DLIN sees ALL the mobility gain due to lower R_EXT

• Strained silicon allows for improved

(25)

25

Delaying Forever…

• New materials & structures can extend Moore’s law

– Strained silicon is a key example

10 100 1000

1990 1995 2000 2005 2010

G

Gordon Moore

(26)

Acknowledgements

The authors gratefully acknowledge the many

people at Intel who contributed to the successful implementation of strained silicon for the 90nm CMOS technology node, including individuals from the following organizations:

• Portland Technology Development

• Technology Computer Aided Design

(27)

27

For further information on Intel’s silicon technology

please visit the Silicon Showcase at