D ESIGN OF L OW IPN F RACTIONAL -N PLL AND B UILDING B LOCKS

4. DESIGN OF LOW PHASE NOISE FREQUENCY SYNTHESIZERS FOR 5G

4.4 D ESIGN OF L OW IPN F RACTIONAL -N PLL AND B UILDING B LOCKS

2f

_REF

f

_DIV

CP

OUT

V

TUNE

f

_PLL

LC-VCO PFD/ CP

Frequency divider ( /N )

DSM

OUT

<1:0>

DSM

IN

<19:0> DSM

Buf.

R2 C2

C1 C3

R3

C4 R4

Loop filter (LF)

C1 C2 R2 R3 C3 R4 C4

12 pF 262 pF 11 k Ω 7 k Ω 2.7 pF 7 k Ω 2.7 pF

Values of Loop components

Figure 83. Overall architecture of the implemented fractional-N PLL

Figure 83 shows the overall architecture of the fractional-N PLL that generates low-IPN signals around 3 – 4 GHz, using the 2fREF-reference clock generated from the preceding RFD. The PLL is based on a conventional 5^th-order and type-II PLL architecture with a 3^rd-order 1-2 MASH DSM. The loop bandwidth of the PLL was designed to be 500 kHz; this wide loop bandwidth is helpful in further suppressing the phase noise of the VCO. The reason we can use this relatively wide loop bandwidth is that the proposed RFD provides the PLL with a frequency-doubled reference clock with very low phase noise. Due to this high reference frequency, the divider can have reduced division number, thereby suppressing the increase in the in-band noise from loop-building blocks, such as a charge pump (CP), a phase-frequency detector (PFD), and a divider. In addition, the quantization noise, Q-noise, from the DSM will be suppressed naturally. The PLL has a 4^th-order passive loop filter. In this type of loop filter, the characteristics are determined mainly by R2, C1, and C2. The values of the passive components are listed in the table. To filter out high-frequency noise coupled through the long metal line from the loop filter to the VCO’s control voltage, VTUNE, an additional 2^nd-order RC filter was placed right before the VTUNE node of the VCO in the layout. This 2^nd-order RC filter, consisting of R3, C3, R4, and C4, also provides an additional rejection to the level of the reference spur and can be used to calibrate the phase margin of the loop.

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V

_TUNE

M

^M

C

^BANK

C

^VAR

M

^P

L

8 bit

2 bit

I

_VCO

Figure 84. NMOS-type cross-coupled LC VCO

Figure 84 shows that the designed NMOS-type cross-coupled LC VCO [48], [49] to achieve low phase noise with a large output swing. To ensure its reliability, the core transistors of the VCO, i.e., MP

and MM, were designed with thick-oxide transistors having 70-μm width and 280-nm length. We used an eight-bit capacitor bank with metal-oxide-metal (MOM) capacitors to increase the frequency-tuning range. We also used a two-bit varactor bank to fine tune the frequency, and it controlled the voltage-to- frequency gain (KVCO). The inductance of the two-turn inductor of the LC tank is 1.2 nH, and the loaded Q is 16.6 at 3.9 GHz. The PFD has a typical rising edge-triggered tri-state topology, and it includes two D-flip flops (DFFs), an AND gate, and delay cells that provide a reset delay to prevent the dead-zone effect. According to a two-bit control signal, the reset delay can change between 150 and 450 ps with steps of 100 ps. As shown in Figure 85, the CP is based on a current-steering topology [28] for higher switching speed and to improve the linearity, and the CP current, ICP, is 200 μA. One of the major causes of the reference spur in the PLLs using a current-steering CP is the skew between the PFD’s output signals, i.e., UP (or DN) and UPb (or DNb), which control the main and the dummy switches of the CP.

To minimize the skews between UP and UPb and DN and DNb, inverter-based latches are used between the PFD and the CP. The CP includes two OP amps, i.e., OP1 and OP2. First, the unit gain OP amp of OP1 is used to fix the voltage of node X at that of the CP output, CPOUT. Since the voltages at nodes X and CPOUT are the same, the voltages at nodes Y and Z do not fluctuate despite the toggling between UP and UPb or DN and DNb, which enhances the switching speed and the linearity of the CP.

106

I

CP

CP

OUT

UPb

DN

UP UPb

UP

DN DNb

Current leaker

IS<0> IS<1>

Dummy SW

20μA 40μA DNb

I

UP

I

DN

OP

₂

OP

1

X

Y

Z

Figure 85. Schematics of the current-steering charge pump (CP)

Second, OP2 is used to implement a dynamic bias control scheme, and it can reduce the mismatch between the up current, IUP, and the down current, IDN, [50]. According to the results of the post-layout simulations, the mismatch between IUP and IDN can be restricted to less than 0.1% across the ranges of CPOUT from 0.38 to 0.95 V. In general, the linearity of the CP tends to be degraded near the point at which the phase difference between SREF and the feedback signal close to zero. To enable the CP to operate in a linear region by shifting the operating point, optional sinking current sources are reserved at CPOUT. Considering the maximum change of the DSM code, the period of the VCO’s output signal, the period of the reference clock, and the division number of the PLL, the required current range is from 28.5 to 44.4 μA. By a two-bit control signal, IS<1:0>, the amount of the sinking current can be changed from 20 to 60 μA.

Figure 86 shows the schematics of a 20-bit 3^rd-order 1-2 MASH DSM, which can provide a 3^rd- order noise-shaping of the quantization noise. Since the DSM generates a two-bit output signal, DSMOUT<1:0>, it causes smaller phase shifts than the 1-1-1 MASH DSM that generates a three-bit output signal. To add a dithering effect, the output of a 15-bit pseudo-random binary sequence (PRBS) generator is connected to the LSB of the DSM code, DSMIN<19:0>.

107

15b PRBS

f

DIV

2

^nd

-order 1-bit DSM

Combiner

DFF

Σ Σ

DFF

Σ Σ DFF

Quantizer Σ

DFF

1

^st

-order 1-bit DSM

f

DIV

f

DIV

f

DIV

DSM

_IN

<19:1>

DSM

_OUT

<1:0>

Σ

DSM

IN

<0>

Figure 86. 3^rd order 1-2 MASH DSM with a 15bit PRBS generator

108