5. DESIGN OF −40 DBC IPN MMW FREQUENCY SYNTHESIZER USING DIGITAL SSPLL · 115
5.2 O VERALL A RCHITECTURE OF THE P ROPOSED SSPLL- BASED F REQUENCY S YNTHESIZER 116
Digital SSPLL-Based mmW-Band Frequency Synthesizer
Smm_OUT
SSSPLL
Optimal BW of SSPLL
PN
20logN1
20logN2
GHz VCO mmW VCO
SREF
Wide BW of mmW ILFM
f
-
Low-in-band PN by an SSPLL at the first stage BW optim. & Q-noise minimization by OSVC-
Wider capture range than mmW-band SSPLLs
-
Ultra-low-IPN mmW signal by wideband mmW ILFM
-
Smm_OUT
SH SREF
Digital SSPLL
DLF OSVC
SBUF BUF
SSSPLL
GHz VCO
fSSPLL= 3.0Ě4.3GHz
fmm_OUT
= 28.0Ě31.0GHz fREF = 100MHz
fmm_OUT = N2 x fSSPLL fSSPLL = N1 x fREF
mmW-band Quad. ILFM
(a)
VREF
K +VTH
ĚVTH
±1 ±1, ±3
DVC K·DVC
±K, ±3K SREF
SBUF
K Optimization
VTH Optimization
±1
±1 OSVC V SH
Optimally-Spaced Voltage Comparators (OSVC) with K & V
THCo-Optimization
−K +3K
−3K +VTH
ĚVTH
VERR
+K K·DVC
(=VSH ĚVREF) +1
−1
−3
+3
Min. Jitter w/ Optimal K
K VTH
RMS Jitter
1bit VC w/
K optimiz.
¢ OSVC w/
K & VTH Co-optimiz.
£
Min. Jitter w/
Optimal K & VTH
SH
(b)
Figure 94. (a) mmW-band frequency synthesizer based on the digital SSPLL using the OSVC (b) the concept of an OSVC-based digital SSPLL with VTH and K co-optimization (bottom)
This work proposes a digital SSPLL-based 28 − 31GHz frequency synthesizer (FS) that can achieve 76fs-RMS jitter and –40 dBc IPN by using the reference frequency of 100 MHz. As shown in Figure 94(a), as the first stage, the digital SSPLL generate GHz-range output signals, thereby, to secure a wide capture range. For the implementation of the digital SSPLL, the optimally-spaced voltage comparators (OSVC) is proposed to overcome the trade-off regarding the Q-noise in the conventional
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digital SSPLLs. For the Q-noise minimization in the proposed OSVC, only three simple 1bit voltage comparators (VCs) are needed instead of high-performance ADC requiring a high resolution and multiple bits. Thus, the proposed work can save significant power and silicon area. Since a bandwidth of the injection-locked frequency multiplier (ILFM) following the digital SSPLL is greater than 200 MHz, the out-band phase noise of the mmW-band signal also is determined by a high-Q VCO of the GHz-range SSPLL rather than the low-Q VCO of the mmW in the ILFM. Consequently, this work can generate mmW-band output signals having ultra-low IPN and RMS jitter.
In the design of TDC-based digital PLLs, it is important to minimize the Q-noise while minimizing the power consumption. As a solution, [56] presents to use a simple BBPD instead of a complicate TDC along with the loop gain optimization of the PLL by controlling the error-correction gain, K, in the background. Even though [56] exhibits excellent power and area efficiency, it has a limitation in terms of the Q-noise minimization. This is because of a lack of information by BBPD, which only has binary information regarding the phase error. To address this limitation, [57] presented a solution, which uses three BBPDs connected in parallel and optimize the spacing between the time thresholds between BBPDs as well as K. Since to defince the thresholds is more suitable for voltage domain rather than the time domain, we apply the concept in [57] to the design of the ditial SSPLL, which is the proposed OSVC-based digital SSPLL. Figure 94(b) shows the output jitter of a 1bit-VC-based digital SSPLL. As shown, if the K is optimized by the background calibration, it can achieve a low RMS jitter performance by effectively suppressing the Q-noise. The figure also shows the OSVC-based ditial SSPLL can achieve a better RMS jitter by co-optimizing the voltage threshold value between VCs, VTH, and K. In the conceptual diagram of an OSVC-based digital SSPLL shown in Figure 94(b), a sample-and-hold (SH) circuit samples the level of SBUF and outputs VSH, which is VSH is compared with VREF by the three VCs having different input offsets, i.e., +VTH, 0, and –VTH, which had been inserted intentionally. Then, the voltage error, VERR, is converted one of the four values of DVC. Lastly, the OSVC can minimize instantaneous phase errors more precisely and the Q-noise, concurrently, with the optimized VTH and K.
Since the delta-sigma-based DACs (ΔΣDACs), which can provide a fine resolution, can be used to calibrate VTH, the concept of the OSVC is more effective in the voltage domain than the time domain.
118 OSVC
Quad.
ILFM VCL
VCH
fSSPLL/8
Digital SSPLL Using OSVC
fSSPLL= 3.3Ě4.3GHz
fmm_OUT= 28.0Ě31.0GHz
Q±
DM (±1) I±
DK SREF
13
2
17 17 DH (±1) 17
VSH,P
VSH,N ΔΣDAC
Loop-Gain Optimizer KI ACC
SREF
VH VM
KP
VLVM
VCM
VTH-Controller VL VM VH
DVC
mmW-Band Frequency Synthesizer Based on Digital SSPLL Using OSVC
*VTH+=VHĚVM
*VTH–=VMĚVL
Diff.
SH
VTH–
VTH+
VTH-Generator
(±1, ±3)
DLF
Smm_OUT SSSPLL
SBUF,N
SBUF,P
ΔΣDAC
DL (±1)
CBANK 9 bits 2 bits
BUF
LC VCO
CVAR
LMAIN
LTAIL
Figure 95. Overall architecture of the mmW-band frequency synthesizer
Figure 95 shows the overall architecture of the mmW-band frequency synthesizer, including the OSVC-based digital SSPLL and the mmW ILFM [21]. In the digital SSPLL, the three voltage comparators quantizes the difference between VSH,P and VSH,N, which are the differentially sampled voltages by the SH. The quantized output values of VCH, VCM, and VCL are DH, DM, and DL, respectively. As shown, the OSVC has four decision values in DVC by placing the offset voltage of VTH+
to the positive input of VCH and that of VTH– to the negative input of VCL. As shown in Figure 96(a), two input offset voltages should be adjusted independently by using the three voltages provided by the VTH-controller, VH, VM, and VL to optimize VTH+ and VTH– even with the presence of the intrinsic input offsets of the VCs. By referring [57], the value of VH and VL can be optimized by the VTH-controller;
when the the optimal values of NTH+ and NTH– are compared with the accumulated values of DH and DL, respectively. The the combination of a ΔΣDAC and the low-pass filters allows VH and VL to have a high resolution, i.e., effectively 10 fs in time domain. VM is the reference value and it is the half of DAC supply voltage. Note that, if the output of ΔΣDAC is monotonous, the input offsets of the three voltages comparator and the non-linearity of the ΔΣDAC have no problem due to the continuously optimized and back-ground calibrated values of VTH+ and VTH–. The digital loop filter consists of the proportional (P) and the integral (I) paths. As shown, the VCO is controlled separately by both paths to minimize a latency, which could degrade the jitter performance. As shown in Figure 96(b), by ensuring zero autocorrelation of DM [56], the loop-gain optimizer can keep adjusting the P-path gain, KP, to be optimum. The settling time of KP is less than 750μs at the worst case.
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D
HN
TH+f
SSPLL/8
7
7
7
V
MD
LACC
RST
N
TH–RST
ACC
7S
REF17 17
7bit Counter
V
HV
LACC ACC
1
1
ΔΣDAC
(a)
D M
t
Too High Loop Gain
Too Low Loop Gain
Optimum Loop Gain
D M z Ě 1 ACC D K
13
(b)
Figure 96. (a) the schematics of the VTH-controller and (b) loop-gain optimizer
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5.3 Operation of the Proposed SSPLL-based Frequency Synthesizer
VTH addition
& decision VTH
update
Operation of Digital SSPLL Using OSVC
ɸ1
ɸ2
ɸ3
SREF
t VC,H+
VC,L+
VSH,P VSH,N
Sampling VTH
update
VTH addition
& decision
VTH–
DVC=1 DVC=3
VTH+
Phase: Sampling
Decision Decision
Sch. of VC
VIN− VIN+
CLK CLK
VOUT
CLK
VTH+ VTH–
(a)
VSH,P
Schematics of V
TH-Generator and Differential SH
SBUF,P SREF
SBUF,N
VSH,N
Dummy SH Dummy
SH
VH
VTH+
VM
VC,H– VC,H+
VTH update
Operation of V
TH-Generator
VTH addition
ɸ1
t V
VTH+
VSH,P VC,H–
VTH+
VC,H+
ɸ1
VSH,P
ɸ2
ɸ2
VCH
DVC VH
CTH–
VM
VCM
VCL ɸ3
ɸ3
ɸ3
VM
ɸ1 ɸ1
ɸ1
ɸ3
CTH+
CTH+
ɸ1
ɸ2
VTH+
ɸ1
VSH,P
CTH+
ɸ1
ɸ2
ɸ2 ɸ3
ɸ3
VL
SREF
SREF
VTH-generator Diffential SH
ɸ1
SH VC,H– VC,H+
VCH
VCH
VC,H+
VC,H–
VC,L+
VC,L–
(b)
Figure 97. (a) Operation of the proposed digital SSPLL using the OSVC (b) the schematics and operation of the OSVC
Figure 97(a) and (b) shows the operation of the proposed OSVC-based SSPLL in the time domain and the schematics of the differential sample-and-hold circuits and the following VTH-generator, respectively.
The overall operation is as follows. First, the sampling of VSH,P and VSH,N is happend by the sample-and- hold circuit at the falling edge of SREF. Second, in ‘VTH update’ phase, i.e., during ɸ1, the voltage difference across CTH+ (or CTH–) is redefined by the outputs of the VTH-generator, VH and VM (or VM and VL), to update the value of VTH+ (or VTH–). Third, in ‘VTH addition’ phase, i.e., during ɸ2, the connection between VC,H– (or VC,L–) and VSH,P (or VSH,N) is rebuilt to add VTH+ (or VTH–) to the input of VCH (or VCL).
Finally, in ‘Decision’ phase, i.e., at the rising edge of ɸ3, decisions are happened by the three voltage comparators to provide DVC. Note that, in the design of the VTH-generator, the sizes of the switches and that of the input transistors of the voltage comparators are minimized and optimized to minimize the
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charge-sharing effect, which is usually occurred by the parasitic capacitors. If the charge-sharing effect is severe, it could degrade the gain of the sample-and-hold circuits. The voltage comparators were implemented based on a double-tail regenerative topology.
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