Before introducing the design of the proposed low phase noise frequency synthesizer, the fundamentals of the frequency synthesizer and the LC VCO are discussed in Chapters 2 and 3 respectively. Finally, Chapter 9 concludes this thesis with a summary of the proposed design of frequency synthesizers for 5G mobile systems.
INTRODUCTION
M OTIVATION AND O BJECTIVE OF R ESEARCH
As the proportion of parasitic capacitance in the LC tank increases for the same resonant frequency, VCOs generating mmW signals cannot achieve a wide frequency tuning range [20]. A prototype has been implemented to demonstrate the feasibility of low phase noise frequency synthesizers in the mmW band based on a cascaded architecture.
T HESIS O RGANIZATION
FUNDAMENTALS OF PLL-BASED FREQUENCY SYNTHESIZERS
B ASIC C HARACTERISTICS
- Basics Operation of PLL
- Key Metrics of the PLL
In the time domain, phase noise corresponds to jitter, deviations from the ideal periodicity of the signal. To estimate the degree of excitation due to a modulating signal, we first need the theory of frequency modulation (FM) [24].
PLL M AIN B UILDING B LOCKS
- Phase-Frequency Detector and Charge Pump
- Loop Filters
- Voltage-Controlled Oscillators (VCOs)
- Frequency Dividers
Note that the coefficient for the null is independent of the order of the loop filter. Two approaches to suppress DSM noise; (a) increases the operating frequency of the DSM (b) decreases the bandwidth of the PLL.
PLL A NALYSIS
- PLL Modeling with Transfer Functions
- Phase Noise Analysis
- Stability
With the output-referenced noise of each building block and the transfer function derived in the previous section, phase noise of the fractional-N CP PLL can be investigated. Figure 48(b) shows the output related phase noise of the VCO, Sn,OUT,VCO with the phase noise of the free running VCO. The NTF of the DSM, NTFDSM(s) and the output related phase noise of the DSM can be written as.
Figure 50(b) shows the output related phase noise of the DSM, Sn,OUT,DSM according to the order of the DSM.
FUNDAMENTALS OF LC VCO
LC R ESONATOR OF LC VCO
- Basics of LC Tank
- Integrated Inductor
- Integrated capacitor
For general LC VCO operating at different GHz, the Q-factor of the inductor dominates the Q-factor of the tank. In the next session, details of the inductor along with the Q factor will be detailed. In addition, the MIM capacitor has a high density, i.e. the capacitance per area, which means the effectiveness of the capacitor (usually about 2 fF/μm2).
Therefore, the unit capacitance of the MOM capacitor may be small compared to the MIM capacitor.
D ESIGN C ONSIDERATIONS
- Start-up Condition
- Topologies of LC VCO
Architecture of NMOS-type cross-coupled LC VCO with steady-state current waveform. Architecture of CMOS-type cross-coupled LC VCO with steady-state current waveform. For a CMOS-type cross-coupled LC VCO, the optimal bias point for the tail current is at the edge of the current-limited region.
In summary, the characteristics of NMOS type and CMOS type LC VCO are summarized in Table 12 below.
P HASE N OISE
- Linear-Time Invariant Model: Lesson’s equation
- Linear-Time Variant Model: Impulse-Sensitive Function
The effect of ∆V on the phase of the LC VCO varies according to the time the current noise is injected, τ, and the reason is intuitively shown in Figure 70(a) and (b). a) Impulse response of the output signal of LC VCOs when the impulse occurs at the peak of the output signal. As shown in Figure 70(a), if the current noise is injected when the VCO output signal is the peak, the noise only changes the amplitude of the output signal and the phase is not distorted. Therefore, the results of the impulse response can be divided into the amplitude variations and the phase variations as shown in Figure 70(b).
However, as shown in Figure 71(a), if the current noise is injected at the zero-crossing point of the VCO output signal, the noise deviates the phase of the output signal from the ideal position, while the amplitude is not distorted.
DESIGN OF LOW PHASE NOISE FREQUENCY SYNTHESIZERS FOR 5G
O BJECTIVE AND M OTIVATION
During the development of mobile communications, the key principle of the industry has been to operate with previous standards and spectrum, which is called backward compatibility or interoperability. Therefore, considering the interoperability with existing standards and the dual connectivity of the practical 5G model, it is important for 5G transceivers to support multiple frequency bands in an efficient manner. Recent PLLs phase noise is plotted and summarized in [17] by normalizing the values of the phase noises to the same frequency.
The proposed RFD increases the reference frequency, which suppresses the level of the in-band phase noise and the delta-sigma modulator (DSM) noise of the PLL.
O VERALL A RCHITECTURE OF THE P ROPOSED LO G ENERATOR
In this design, the frequency bands marked in the dotted box in Figure 74 were implemented to verify the feasibility of the approach. As a result of this increase in the reference frequency of the PLL, the in-band phase noise and the quantization noise of the DSM of the PLL can be significantly suppressed. When one of the two ILFMs is selected to be used, the four signals in quadrature relationship as output from the divide-by-2 divider after the PLL are transferred to pulse generators (PGs), which generate injection pulses that are injected into the quadrature VCOs (QVCOs).
Since both ILFMs share one FTL, the overhead such as power consumption or silicon area for designing multiple ILFMs is greatly reduced.
As shown above, the magnitude of the change in duty cycle depends on the amount of delay through the slow current path. Duty Correction Logic (DCL) algorithm to decode CDCC<6:0> to reduce redundant delay and thus added noise. Changes in SO,5 and SDZ duty cycles, depending on DCCL operation.
Since the error in the duty cycle of SO.5 in the dead zone cannot be corrected, the resolution of the DCCL is determined by the size of the dead zone.
D ESIGN OF L OW IPN F RACTIONAL -N PLL AND B UILDING B LOCKS
One of the main causes of reference excitation in PLLs using CP for current control is the mismatch between the PFD output signals, ie. UP (or DN) and UPb (or DNb), which control the main and virtual switch CP. First, the unity gain of the OP amp OP1 is used to determine the node X voltage at the CP output, CPOUT. Since the voltages at nodes X and CPOUT are the same, the voltages at nodes Y and Z do not fluctuate despite switching between UP and UPb or DN and DNb, which increases the switching speed and linearity of CP.
In general, the linearity of the CP tends to deteriorate near the point where the phase difference between SREF and the feedback signal approaches zero.
D ESIGN OF L OW IPN F RACTIONAL -N PLL AND B UILDING B LOCKS
After that, the values of the two ranges are converted to the corresponding DC voltages, VAQ+ and VAQ−, and the loop monitors the voltages in real time. Since the FTL only operates at low frequency by monitoring phase deviation averages, the power consumption of the FTL was less than 900 μW. Although we used two QVCOs in this work, the occupied area was not large because the size of the inductors in both ILFM_x3 and ILFM_x15 was small.
The number of turns of the inductor in ILFM_x3 was three and the inductor of ILFM_x15 is inherently small due to its high oscillation frequency.).
E XPERIMENTAL R ESULTS
Measured level of the reference spur reduction at the output of the PLL when DCCL is enabled. Phase noise measurement at the fractional N-mode PLL with output from the ILFM_x3 and ILFM_x15. Measurement of phase noise when the PLL is in integer-N mode with output from the ILFM_x3 and ILFM_x15.
In Figure 92 the measured phase noise of the PLL in the fractional-N mode together with the output signals of ILFM_x15 and ILFM_x3.
C ONCLUSIONS
DESIGN OF −40 DBC IPN MMW FREQUENCY SYNTHESIZER USING DIGITAL SSPLL · 115
O VERALL A RCHITECTURE OF THE P ROPOSED SSPLL- BASED F REQUENCY S YNTHESIZER 116
For the implementation of digital SSPLL, optimally spaced voltage comparators (OSVC) are proposed to overcome the trade-off regarding Q noise in the conventional one. The PK settling time is less than 750μs in the worst case. a) VTH controller schematics and (b) loop gain optimizer. Schemes of VTH-Generator and Differential SH. a) Operation of the proposed digital SSPLL using OSVC (b) schematics and operation of OSVC.
Figure 97(a) and (b) shows the operation of the proposed OSVC-based SSPLL in the time domain and schematics of the differential sample-and-hold circuits and the following VTH generator, respectively.
E XPERIMENTAL R ESULTS
When the reference frequency fREF was 100 MHz, (a) measured phase noise and output signal spectra of 3.8 GHz digital SSPLL based on OSVC (b) measured phase noise. Measured phase noise and spectrum of the 28.5 GHz signal of the proposed mmW-frequency synthesizer. As shown in Table 14, the proposed digital SSPLL achieved the lowest RMS jitter among the state-of-the-art SSPLLs.
In addition, this work achieved the best FONT,AND (normalization of COMMIT to FRED) and the best FOMJIT among the state-of-the-art mmW frequency synthesizers.
C ONCLUSIONS
DESIGN OF WIDEBAND AND LOW PHASE NOISE QUADRATURE LO-GENERATOR 128
- Overall Architecture of the Proposed Quadrature LO-Generator
- Limitations in Conventional Divide-by-3 Dividers
- The Proposed Differential Divide-by-3 Divider with 50% Duty-Cycle
As shown in Figure 105, the divisor of dividing by 6 consists of the proposed differential divisor of dividing by 3 with a duty cycle of 50% and the following conventional divisor of dividing by 2. Figure 107(a) and (b) show the implementation and timing diagrams of the proposed fully differential divide-by-3 divider with 50% duty cycle, respectively. Therefore, under all circumstances, the DPC can safely correct any incorrect operations of the proposed differential divide-by-3 divisor.
Monte-Carlo simulations: I/Q phase errors between quadrature signals of the proposed divider by 6 over the target frequencies.
- Design of the LC VCO
- Design of the Low-Dropout Regulator
Due to the proposed LO plan, the required FTR of the VCO was reduced from 63% to 39%. Along with small capacitive loading, the LC-VCO can maximize the tank's loaded Q, enabling the VCO to achieve low phase noise. The core current for the LC-VCO, ICORE, was taken from the LDO at the top.
The RC filter at the input of the error amplifier had a pole frequency of 1.1 MHz by including a 3-kΩ resistor and a 50-pF MOS capacitor.
E XPERIMENTAL R ESULTS
The corresponding FTR for the VCO was 52%, which is sufficient to cover the target FTR. To verify that all required LO frequencies can be generated by the proposed LO generator, the spectra of each divider's output were measured. Measured spectra of the proposed LO generator using (a) the divider by 4 (b) the divider by 6 and (c) the divider by 12.
As shown in Figure 120(a) – (c), the phase noise of the proposed LO generator was low enough to meet the phase noise requirements of cellular standards.
C ONCLUSIONS
DESIGN OF WIDEBAND DUAL-MODE LC VCO WITH A SWITCHABLE CORE
- O BJECTIVE AND M OTIVATION
- F REQUENCY -R ANGE A NALYSIS OF AN LC VCO
- Lower Boundary of the Oscillation Frequency by the Start-Up Condition
- Upper Boundary of the Oscillation Frequency by Parasitic Capacitance
- P ROPOSED D UAL -M ODE LC VCO W ITH A S WITCHABLE G ATE -B IASED A CTIVE C ORE
- Proposed Dual-Mode VCO: HF and LF Modes
- Switch-Size Minimization by the Gate-Bias Technique
- Phase Noise of the VCO
- E XPERIMENTAL R ESULTS
- C ONCLUSIONS
Therefore, the differential signals from the primary core cannot reach the secondary core. In HF mode, the operation of the LC-VCO is exactly the same as the conventional LC-VCOs. Therefore, in LF mode, the minimum oscillation frequency of the LC-VCO can theoretically be further reduced by more than 20%.
By considering the effect of Rb, the phase noise of the LC-VCO can be predicted as [32].
DESIGN OF MULTI-CLOCK GENERATOR
- O BJECTIVE AND M OTIVATION
- C ONCEPT OF THE P ROPOSED M ULTI -F REQUENCY G ENERATOR
- I MPLEMENTATION OF H IGHLY -D IGITAL M ULTI -F REQUENCY G ENERATOR
- Implementation of the Overall Architecture
- Out-Edge Selection Logic and the Test Edge Generator
- Digitally-Controlled Oscillator and Fractional Injection Logic
- A NALYSIS OF F REQUENCY M ISMATCHES B ETWEEN DCO S AND P HASE N OISE
- Analysis of Frequency Mismatches Between the DCOs
- Analysis of Phase Noise of the Multi-Frequency Generator
- E XPERIMENTAL R ESULTS
- C ONCLUSIONS
The TIC sequentially calibrates each DCO's output frequency in the background using the replica DCO. Similar to the architecture of Figure 133(c), the bandwidth of the TIC cannot be widened since the TIC calibrates the DCOs in a time-scrambled manner. Second, M output signals of the ILMFG can achieve ultra-low jitter, since the injection-lock bandwidth has no relation to that of the TIC.
Based on the value of SPD, FCWk,UPD<9:0> is calculated by REGOUT and updated accordingly.
CONCLUSIONS
