O BJECTIVE AND M OTIVATION

8. DESIGN OF MULTI-CLOCK GENERATOR

8.1 O BJECTIVE AND M OTIVATION

Modern system-on-chip (SoC) includes various modules, which perform a number of functions, such as memory, input/output (I/O) interfaces, microprocessors, and the power management. To simultaneously improve overall system performance with high energy efficiency, each module must operate at a unique optimum clock frequency. [109] – [114]. In addition, for optimizing the overall system performance and the energy efficiency, multiple clock frequencies, whose frequency can be changed dynamically with fine resolution, are required in advanced multicore processors [115]. When considering a solution that generates multiple clock frequencies, the prerequisite is to sustain low phase noise performance of the output signal of each clock, without excessively high power consumption and huge silicon area [113], [116]. Figure 133(a) shows the simplest architecture using multiple phase- locked loops (PLLs), which are connected in parallel. Since this approach requires multiple PLLs to operate simultaneously, a significant amount of power will be consumed and a large silicon area will be occupied, which conflicts with previous prerequisites. In contrast to this one-dimensional approach, [117] proposed a new architecture, which is shown in Figure 133(b). Here, only a single fractional-N PLL is used and there are subsequent frequency dividers having a fractional resolution. Each frequency divider includes a delta-sigma modulator (DSM) and a circuit to remove a quantization-noise (Q-noise), i.e., Q-noise canceler. Compared with the architecture in Figure 133(a), it overwhelms the previous one in terms of power consumption and silicon area since it has only one PLL.

f

_REF

f

M

f

₁

f

₂

PLL 1

PLL 2

PLL M

(a)

171

f

₀

f

₁

ADPLL

Fractional Divider &

Q-noise Canceler f

₂

f

_M

f

₀

š f

₁

, f

₂

, ···, f

_M

f

_REF

PLL

(b)

TDC

f

₁

f

₂

f

_M

f

_REF

DLF 1

DLF 2

DLF M

/N

(c)

Figure 133. Conventional architectures providing multiple outputs with different operating frequency:

(a) multiple PLLs in parallel; (b) a single PLL with subsequent multiple fractional dividers with a fractional resolution; (c) digital PLL includes multiple DCOs, which are corrected by a single TDC

However, since the operating frequency of the output signal decrease as the frequency passes through the frequency dividers, the PLL operating frequency, f0, by considering the division ratio of the divider, the operation frequency must be higher than the required frequencies. Therefore, additional power is consumed by the PLL. In addition, the Q-noise canceller along with the DSM increases the complexity of the design and the operation of the frequency dividing requires more power consumption.

Alternatively, a multi-frequency generator can be designed in a digital fashion as in Figure 133(c), which includes a time-to-digital converter (TDC) and multiple pairs of a digitally-controlled oscillator (DCO) along with a digital loop filter (DLF). Only a single TDC is connected to the DCOs and it sequentially calibrates the frequency drifts of each DCO. Since the required number of TDC is only one to corrects all DCOs, this architecture has low complexity and small the power consumption compared to the architectures in Figure 133(a) and (b). However, when the number of DCOs, M, increases, it implies that the calibration period for each DCO is extended by M times. Thus, the effective comparison

172

frequency seen by each DCO should decrease accordingly, which means the narrowed loop bandwidth.

Therefore, this degrades the phase noise and increases the settling (or locking) time.

In this work, we propose an all-digital injection-locked multi-frequency generator (ILMFG), which simultaneously generates multiple output clocks with an ultra-low-jitter, which operates at different clock frequencies [118]. The concept of the propose multi-frequency generator is illustrated in Figure 134(a). The ILMFG includes the DCO bank having multiple DCOs and a time-interleaved calibrator (TIC). The TIC sequentially calibrates each DCO’s output frequency in the background with the help of the replica-DCO. Similar to the architecture of Figure 133(c), the bandwidth of the TIC cannot be widened, since the TIC calibrates the DCOs in a time-interleaved fashion. But, there are difference from the digital PLL with multiple DCOs shown in Figure 133(c), where the large M degrades the phase noise, the proposed multi-frequency generator in Figure 134(a) can stably provide ultra-low-jitter output signals regardless of the number of M. This is because the injection-lock bandwidth of the DCO can be kept very wide, regardless of M, since the injection pulse is continuously injected into all DCOs at every period of the reference clock, i.e., the bandwidth of the TIC and that of the injection-locking have no relationship. Thus, as drawn in Figure 134(b), the injection-locking can suppress the phase noise (or jitter) dramatically up to its bandwidth, which is typically wide [119], [120]. Here, the main purpose of the calibrator is not only to reject DCOs’ noise but also to calibrate the frequency drifts in DCOs [46], [89], [90], [121], [122], [123], [124] – [127], which doesn’t need to have wide bandwidth. Therefore, the bandwidth of the TIC need not be wide if that bandwidth can track the variations in the supply voltage or the temperature. In addition, the proposed clock generator can have a fractional resolution for the multiplication factor, by the fractional injection logic [128], which rotationally injects the injection pulses into the ring DCO’s nodes.

173

f

1

f

k

f

M

S

REF

(f

REF

)

Rotating every 2T

_REF

Under Calibration (1 ≤ k ≤ M)

f

M-1

DCO

1

DCO

k

DCO

M-1

DCO

M

DCO Bank

Fractional Inj. Logic

PG Replica-DCO (DCO

R

)

Time-Interleaved Calibrator (TIC) FCW

_k

FCW

_k,NEW

S

_INJ

(f

REF

)

(a)

Offset frequency

P ha se no is e

TIC BW

Injection-locking BW ILMFG PN

Free-running VCO PN

Decreased as M increases

Maintained wide irrespective of M

(b)

Figure 134. (a) Conceptual diagram of this work with the time-interleaved calibration (b) how the ILMFG can have low noise with the help of the injection locking

This Chapter is organized as follows. In Chapter 8.2, the concept of this work is introduced along with the proposed calibrator operating in the time-interleaved fashion. Chapter 8.3 explains the implementation of the ILMFG with its operation. Chapter 8.4 describes the effects such as phase noise and the spur, which is raised by the frequency mismatches between DCOs of the DCO bank and the replica-DCO. Chapter 8.5 and 8.6 present experimental results and the conclusions, respectively.

174