6. DESIGN OF WIDEBAND AND LOW PHASE NOISE QUADRATURE LO-GENERATOR 128
6.5 E XPERIMENTAL R ESULTS
Figure 116. Chip micrograph of the proposed quadrature LO-generator
In this work, we proposed a single LC-VCO-based low phase noise and wideband quadrature LO- generator for multi-standard cellular transceivers that was fabricated in a 40-nm CMOS technology.
Chips were tested on printed circuit boards (PCBs) after wire-bonding. Figure 116 shows the chip micrograph of the proposed LO-generator. The active area of the LC-VCO and the LO-dividers was 0.15 mm2. For measurement, quadrature signals from the dividers were transferred to pads through on- chip test buffers and DC-blocking metal-oxide-metal (MOM) capacitors. The on-chip test buffers consisted of cascaded inverters, where their sizes increased gradually to drive 50Ω load impedance.
Figure 117. Measured spectrum of the VCO of the LO-generator
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Figure 117 shows the measured spectrum of the VCO signals, where the frequency range was from 6.76 to 11.51 GHz. The corresponding FTR of the VCO was 52%, which is sufficient to cover the target FTR.
To verify that all required LO-frequencies can be generated by the proposed LO-generator, the spectra of the outputs of each divider were measured. Figure 118(a), (b), and (c) show the spectra of signals from the divide-by-4, the divide-by-6, and the divide-by-12 dividers, respectively. As shown in Figure 118(a) – (c), the proposed LO-generator using a single VCO is capable of covering all LO-frequencies for recent multi-standard cellular transceivers, as shown in Figure 102. Figure 119(a) and (b) show the measured frequency ranges of the VCO signals and the LO-signals, respectively, when the eight bit code of the capacitor bank and the control voltage of the two bit varactor were swept.
(a)
(b)
148 (c)
Figure 118. Measured spectra of the proposed LO-generator using (a) the divide-by-4 (b) the divide- by-6 and (c) the divide-by-12 divider
(a) (b)
Figure 119. Measured frequency ranges of (a) the VCO and (b) the LO-generator
Figure 120(a) – (c) show the measured phase noise of the LO-signals from three dividers. The figures also show phase noise from post-layout simulations, observed at the outputs of the dividers, to evaluate the intrinsic performance of the dividers. In Figure 120(a) – (c), the most stringent spot noise requirements, which come from GSM, were marked: –118, –136, and –151 dBc/Hz at the offsets of 400 kHz, 3 MHz, and 20 MHz, respectively, for the mid-frequency band (MB), and –118, –136, –150, and –162 dBc/Hz at the offsets of 400 kHz, 3 MHz, 10 MHz, and 20 MHz, respectively, for the low-
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frequency band (LB) [74]–[77]. Figure 120(a) shows that the signal from the divide-by-4 divider with a 1.97-GHz LO-frequency achieved a phase noise of –132.4 dBc/Hz at the 1-MHz offset. Figure 120(b) shows that the signal from the divide-by-6 divider with a 1.47-GHz LO-frequency achieved a phase noise of –134.1 dBc/Hz at the 1-MHz offset. In Figure 120(c), the LO-signal from the divide-by-12 divider had a phase noise of –141.0 dBc/Hz at the 1-MHz offset from the 709-MHz LO-frequency. In this measurement, the VCO with the VCO buffer, and the divide-by-12 divider consumed 13.0 and 3.5 mW, respectively. As shown in Figure 120(a) – (c), phase noise of the proposed LO-generator was sufficiently low to satisfy the phase noise requirements of cellular standards. Figure 121 shows phase noise at the offsets of 400 kHz, 3 MHz and 10 MHz over all target LO-frequencies with the GSM requirements, indicated by the dotted lines. The high-frequency band (HB) is only used for LTE, where critical phase noise requirements are defined as integrated phase noise (IPN) rather than as spot noise.
(a)
(b)
150 (c)
Figure 120. Measured and simulated phase noise of LO-signals with frequencies of: (a) 1.95 GHz by divide-by-4, (b) 1.46 GHz by divid-by-6, and (c) 706 MHz by divide-by-12 (at offsets greater than 10
MHz, PN was saturated by the thermal noise of the on-chip test buffer)
Figure 121. Phase noise at three offsets over LO-frequencies for all three bands
Figure 122(a)–(c) show the measured quadrature signals (I/Q signals). The most reliable method to evaluate an I/Q phase error is to measure the sideband rejection of the output of an on-chip quadrature mixer that receives the quadrature signals from the LO-generator [97]. However, since a quadrature mixer was not integrated in this work, I/Q phase errors were obtained from the signals, acquired through time domain measurements using an oscilloscope. To minimize potential phase errors due to any extrinsic causes in measurement, the lengths of the transmission lines and the bonding wires for quadrature signals were carefully matched when PCBs were implemented. Figure 122(a) shows the I/Q signals with a 2.38-GHz LO-frequency from the divide-by-4 divider with the phase difference of 89.5°.
Figure 122(b) shows I/Q signals with a 1.433-GHz LO-frequency from the divide-by-6 divider with a
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phase difference was 89.4°. In Figure 122(c), the I/Q signals with a 709-MHz LO-frequency were generated from the divide-by-12 divider, and the phase difference was 90.7°.
(a)
(b)
(c)
Figure 122. Measured quadrature (I/Q) signals: (a) Divide-by-4; (b) divide-by-6; (c) divide-by-12
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Table 16 compares the performance of the proposed LO-generator with state-of-the-art wideband quadrature LO-generators. Reference [80], [84], [88], [89] show larger frequency ranges, since they targeted software-defined radio or cognitive radio applications. Compared to the architectures that used two LC-tanks, the proposed LO-generator occupies a smaller silicon area. It also had the lowest normalized phase noise while consuming low power, since the VCO was able to maximize its loaded Q due to the relaxed FTR, and the TSPC DFF-based LO-dividers achieved low phase noise, irrespective of variations in PVT. In addition, it had small I/Q phase errors over all target LO-frequencies, due to the proposed quadrature divide-by-6 divider using the differential divide-by-3 divider with 50% duty cycle.
Table 16. Performance comparison with state-of-the-art wideband quadrature LO-generators
Process fLO (GHz)
No. of LC-Tank
I/Q Gen.
Method
Area (mm2) (VCO+I/Q Gen.)
PN(dBc/Hz)
@ foff (fLO)
Norm.
PN(dBc/Hz)
@1MHz (1GHz)
Power (mW) (VCO+I/Q Gen.)
I/Q phase error.
[78] 130
CMOS 1.8‒6.0 2 (QVCO)
QVCO +SSB Mixer/
Quad. Dividers
1.28* ‒130.4 @1.6MHz
(1.87 GHz) ‒130.8 23.3 ‒ 35.0 N/A
[80] 90
CMOS 1.0‒10.0 2 (QVCO)
QVCO +SSB Mixer/
Quad. Dividers
0.29 ‒120.0 @1MHz
(1.75 GHz) ‒124.9 31.0 N/A
[81] 130
CMOS 0.87‒2.6 2 (QVCO)
QVCO +SSB Mixer/
Quad. Dividers
0.19 ‒126.5 @1MHz
(1.70 GHz) ‒131.1 27.8 < 2°
[83] 65
CMOS 5.8–9.4 2 (QVCO)
QVCO
(No Divider) 0.35 ‒123.7 @1MHz
(3.80 GHz) ‒134.8 7.6
(VCO Only) < 1.5°
[84] 40
CMOS 0.04‒6.0 2
Quad. Dividers ( 7 Series Div2 Dividers)
0.21* ‒149.0 @20MHz
(3.60 GHz) ‒134.1 30.0
(w/ PLL) N/A
[88] 65
CMOS 4.9–11.1 1 ILRO/
Quad. Dividers 0.11 ‒122.3 @1MHz
(1.61 GHz) ‒126.4 22.0 < 4°
[89] 65
CMOS 0.01‒6.6 1 ILRO/
Quad. Dividers 0.14* ‒135.3 @3MHz
(1.70 GHz) ‒130.4 16.0 – 26.0
(w/ PLL) N/A
This work
40
CMOS 0.56‒2.92 1 Quad. Dividers
Only 0.15
‒141.0 @1MHz
(0.71 GHz) ‒138.0 16.5
< 1°
‒132.4 @1MHz
(1.97 GHz) ‒138.3 16.0
* Estimated from chip photographs
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