Phase-Frequency Detector and Charge Pump

2. FUNDAMENTALS OF PLL-BASED FREQUENCY SYNTHESIZERS

2.2 PLL M AIN B UILDING B LOCKS

2.2.1 Phase-Frequency Detector and Charge Pump

In the PLL system, the main objective is to correct the frequency drifts in the VCO, which means a block that can detect the frequency drifts of the VCO is required. In charge pump (CP) PLLs, a phase- frequency detector (PFD) roles as the detection block. As shown in Figure 20, the PFD consists of two D-flip flops (DFFs) and a NAND gate. The CP consists of two switches and two current sources. The operation of the PFD is comparing the phase of the reference clock, fREF, and that of the feedback clock, i.e., the divided VCO output, fDIV, and then, providing a correction signal to the CP, i.e., SUP and SDN. The CP converts the correction signals to a corresponding amount in the current. As shown, when SUP

is in the high level, SWUP is turned on and the sourcing current, IUP, flows from the supply to the LPF.

When SDN is in the high level, SWDN is turned on and the sinking current, IDN, flows from the LPF to the ground. In this way, the current amount flows to the LPF is adjusted.

f

_REF

f

_DIV

S

_UP

S

_DN

D Q

rst

D Q

rst

CP

_OUT

To LPF

Sourcing current (UP current, IUP)

Sinking current (DN current, I_DN)

SW

_UP

SW

_DN

Phase-frequency detector Charge pump

Figure 20. Simplified block diagram of the PFD and the CP

According to the status of the two inputs of the PFD, i.e., fREF and fDIV, the PFD can have three status, as shown in Figure 21. When the PFD is in the high impedance state if the rising edge of fREF goes into the PFD first, i.e., fREF leads fDIV, the signal of SUP turns to the high level and the sourcing current is enabled. In this manner, if the rising edge of fDIV goes into the PFD first, i.e., fDIV leads fREF, the signal of SDN turns to the high level and the sinking current is enabled. When the PFD detects both levels of SUP and SDN are high, both sourcing and sinking currents are disabled by turning off SUP and SDN.

22

S

_UP

= 0 S

_DN

= 1

(Enabled I

DN

, disabled I

UP

)

S

UP

= 0 S

DN

= 0

(Disabled I

UP

& I

DN

)

S

_UP

= 1 S

_DN

= 0

(Enabled I

UP

, disabled I

DN

)

f

REF

's rising edge

@ low level of f

_DIV

f

DIV

's rising edge

@ low level of f

_REF

f

_DIV

's rising edge f

_REF

's rising edge

High impedance

f

_REF

's rising edge f

_DIV

's rising edge

Figure 21. Operation of the PFD; three status

According to the operation of the PFD described above, the averaged output current of the CP can be drawn over the phase error between fREF and fDIV, Δϕ, as shown in Figure 22, which corresponds to the transfer function response of the PFD and the CP. As shown, the gain of the PFD and the CP, KPFD-CP, can be easily calculated from the slope as follows.

K_PFD-CP

തതതതതതതതതത= I_CPെ ሺെI_CPሻ 2πെ ሺെ2πሻ =I_CP

2π (18)

Assume I

_CP

= I

_UP

= I

_DN

+I

_CP

˰

˰ ^I

CP

+2π +4π

˰4π ˰2π

CP

_OUT

∆ϕ

K_PFD-CP

Gain of PFD+CP

Figure 22. Transfer function of the PFD and CP

23 Practical Issue of the PFD Design: Dead Zone

When the PFD is implemented in real circuits as shown in Figure 23, there is a practical issue which is called as dead-zone. When the PLL reduces the phase error close to zero, due to finite turn-on time of the switches, SWUP and SWDN, the switches can not swiftly response the small phase errors, which means the switches are not fully turned on. Then, the average output current of the CP is almost zero when the phase error is near zero. As a result, the decreased gain of the PFD and the CP incurs the weak suppression of the VCO phase noise. Moreover, the non-linear transfer function of the PFD and the CP, as shown in Figure 23, would degrade the performance of the PLL in term of overall phase noise and fractional spurs.

f_REF

f_DIV

S_UP

SDN

D Q

rst

D Q

rst

CP_OUT

To LPF

Sourcing current (UP current, I_UP)

Sinking current (DN current, IDN)

Phase-frequency detector Charge pump VBP

V_BN

CP_OUT

Dead zone

∆ϕ

Ideal Real SWUP

SW_DN

Figure 23. Real implementation of the PFD and the CP

To solve the problems occurred by dead zone, mainly, there are two solutions; First, at the output of the NAND gate, introduce a delay intentionally, which is greater than the finite turn-on time of the switches.

In this way, when the phase error is close to zero, the average output current can properly respond to the small phase error. However, it could increase the phase noise of the CP. Second, attach a bleed current at the output of the CP. Due to the bleed current, the real transfer function in Figure 23 will shift to left or right along with x-axis. Therefore, we can avoid the dead zone when the phase error is small.

24 Practical Issue of the PFD Design: Cycle Slipping

When phase error is smaller than 2π, the PLL tracks the input frequency variation without no special issue. However, if the phase error is larger than 2π, the phenomenon called a cycle slipping happens [27]. Literally, the cycle slipping means the PFD misses the edges of the reference clock or the divided VCO signal. Figure 24 shows how the cycle slipping happens in the time domain. When fREF is much faster than the divided VCO signal, fDIV, the 5^th edge of fREF at t4 is slipped since the 4^th edge of fDIV is not in between the 4^th and 5^th edge of fREF. Thus, a sudden decrease of the duty cycle of the CPOUT, results in the sudden voltage drop across the loop filter (specifically, across the resistor), which causes slow locking time of the PLL. Note that if the bandwidth of the PLL is wide enough, the PLL can correct the frequency of the VCO before the cycle slipping happens. Figure 25 shows the transient response of the cycle slipping in PLL.

CP

OUT

˰ ^I

CP

+I

_CP

f

_REF

f

DIV

Slipped edge

t0 t1 t2 t3 t4 t5 t6 t7

Figure 24. Timing diagram when the reference clock leads the feedback clock

Time (s)

F req . err o r (H z)

Cycle slippling

By sudden drop of CP

OUT

's duty cycle

Figure 25. Transient response of the cycle slipping

25