1
Strategic EHS
Strategic EHS
Considerations in Selection
Considerations in Selection
of Next Generation Fab
of Next Generation Fab
Materials
Materials
ERC Retreat & IAB Meeting
ERC Retreat & IAB Meeting
Jim Harrison
Jim Harrison
Agenda
Agenda
Business Driver: Moore’s Law
Business Driver: Moore’s Law
Technical Challenges
Technical Challenges
EHS Technical Challenges
EHS Technical Challenges
Other EHS Challenges
Other EHS Challenges
Intel Approach
Intel Approach
August 21, 2003 J Harrison 3
Business Driven by
Business Driven by
Moore’s Law
Worldwide Semiconductor
Worldwide Semiconductor
Revenues
Revenues
$B
$B
1 10 100 1000
August 21, 2003 J Harrison 5
Average Transistor Price By Year
Average Transistor Price By Year
Source: Dataquest/Intel12/02 Source: Dataquest/Intel12/02
0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10
$
$
Transistors Shipped Per Year
Transistors Shipped Per Year
1017
1016
1015
1014
1013
1012 1011
1010
109 Units
1018
August 21, 2003 J Harrison 7
Integrated Circuit Complexity
Integrated Circuit Complexity
1K 1K 4K 4K 64K 64K 256K 256K 1M 1M 16M 16M 4M 4M 64M 64M 4004 4004 8080 8080 8086 8086 80286
80286 i386™i386™
i486™
i486™
Pentium
PentiumPentiumPentium®® ®
®IIII Pentium
Pentium®® III
III
256M
256M 512M512M
Pentium
Pentium®®4 Itanium
Itanium™™
1G
1G 2G2G
4G
4G
128M
128M
MMemoryemory
S
S MicroprocessorMicroprocessor 1965 Actual Data
1965 Actual Data
1960
1960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010
16K
16K
1975 Projection
1975 Projection
MOS Arrays MOS Logic 1975 Actual Data
MOS Arrays MOS Logic 1975 Actual Data
Technical Challenges of
Technical Challenges of
Moore’s Law
August 21, 2003 J Harrison 9
1
1
µ
µ
m
m
2
2
SRAM Cell
SRAM Cell
P501 Contact
P501 Contact
1978
1978
P1262 SRAM Cell P1262 SRAM Cell
2002 2002
1
Age of Nanotechnology
Age of Nanotechnology
10000 10000 1000 1000 100 100 10 10 10 10 1 1 0.1 0.1 0.01 0.01 Micron
Micron NanometerNanometer
1970 1980 1990 2000 2010 2020
1970 1980 1990 2000 2010 2020
Nominal feature size
Nominal feature size
August 21, 2003 J Harrison 11
Intel’s Transistor research down to 10nm
Intel’s Transistor research down to 10nm
Experimental transistors for future process generationsExperimental transistors for future process generations
Experimental transistors for future process generations
32nm process 2009 production
32nm process
32nm process
2009 production
2009 production
22nm process 2011 production
22nm process
22nm process
2011 production
2011 production
We are investigating
several options at <10nm
We are investigating
We are investigating
several options at <10nm
several options at <10nm
65nm process 2005 production
65nm process
2005 production 45nm process
2007 production
90 nm Generation Interconnects
90 nm Generation Interconnects
M7
M6
M5
M4
M3
M2
M1 Low-k CDO
Dielectric
Copper Interconnects
August 21, 2003 J Harrison 13
New Materials and Device Structures
New Materials and Device Structures
Extending Transistor Scaling
Extending Transistor Scaling
Future
Options
Gate
Silicide
Added
Channel
Strained
Silicon
Changes
Made
High-k
Gate
Dielectric
New
Transistor
Structure
Transistor
Minimum Insulator Thickness
Minimum Insulator Thickness
vs Time
vs Time
1 10 100
Oxide Thickness
Oxide Thickness
(Nanometers)
(Nanometers)
1.0µ
1.0µ
0.35µ
0.35µ
0.25µ
0.25µ
0.18µ
0.18µ
0.13µ
0.13µ
Electrical Electrical Physical
August 21, 2003 J Harrison 15
Nanotechnology Environmental
Nanotechnology Environmental
Challenge Drivers
Challenge Drivers
–
–
Increases in:
Increases in:
Manufacturing “Si” Area Manufacturing “Si” Area
Total # of Materials Total # of Materials
New & Novel MaterialsNew & Novel Materials
Industry & Company Industry & Company Unique Materials
Unique Materials
Supply Chain Supply Chain
Globalization
Globalization
PrePre--cursors cursors
Transistor Architecture Transistor Architecture
Options
New Materials
P858 P860 P1262 P1264 (est.)
Technology
Options
Specialty materials evaluated
–2001 hundreds of materials
Other Environmental Challenge
Other Environmental Challenge
Drivers:
Drivers:
Regulation Regulation Globalization
Globalization
“Superset approach”“Superset approach”
CompetitiveCompetitive
Product ecologyProduct ecology
Manufacturing process Manufacturing process Environmental Environmental performance a performance a “competitive issue” “competitive issue”
Community Citizenship Community Citizenship
Recent Concerns Recent Concerns
PFOSPFOS
REACHREACH
Chemical Hazard Chemical Hazard
0 100 200 300 400 500 600 700 800 900
1800 1850 1900 1950 2000 2050
August 21, 2003 J Harrison 17
The EU Legislative Environment
The EU Legislative Environment
Intel takes the European regulatory environment very seriously.
The EU’s legislating of Products has an automatic impact on not only Intel’s largest investment in Europe, our Fabs in Ireland (around € 5 billion by 2005) but also on our
worldwide operations because of Intel’s ‘
Copy Exactly
’ methodology for manufacturing Intel is preparing our programs to satisfy WEEE and RoHS.
Future legislation on the eco-design of products and energy efficiency (EUP) and other areas are in discussion with no data on WEEE and RoHS performance.
Regulatory actions can be burdensome, sometimes overlap and potentially disproportionate to the environmental
problems they are trying to solve
Intel is working with EU regulators and stakeholders to
Intel’s Guiding Principles
Intel’s Guiding Principles
Rationale
It’s the Right Thing to do!
Triple Bottom Line:
Financial Performance –
Return on Investment
Social and Community
Commitments
The Environment –
Natural Resource Sustainability
Part of Intel’s Values
Operational Excellence
Principles
Prevent all injuries in the workplace
Be an ESH leader in our communities and our industry
Reduce the
environmental footprint of our
August 21, 2003 J Harrison 19
What We Do
What We Do
Support & Role Model EHS at the Top
Clear EHS Policy
EHS Goals owned by the EHS Goals owned by the
Operations
Operations
Measure and Report EHS Performance
Extend EHS to Supply Extend EHS to Supply Chain
Chain
“Safety First” & Live It!
Treat the Community as a Customer
EHS Policy Signed by Craig Barrett, CEO
Quarterly EHS
Operations Review
Design for EHS Design for EHS
integrated with integrated with Technology Technology Development Development
Employee surveys demonstrate strong support by
EHS Technology Engagement
EHS Technology Engagement
Model
Model
YEARS to High Volume Manufacturing
Ability to Effect Change
6 4 2 0
Manufacturing Ramp
Supplier R&D
External Research Process Development
Commercialization Phases Demonstration Ramp to HVM
Very early engagement
through universities
and government
labs
Early engage-ment
through tool supplier
targets
Optimum Time to effect change in
technology Technology frozen, major changes require much more effort
- use continuous improvement
Research
August 21, 2003 J Harrison 21
Rapid Technology Changes
Rapid Technology Changes
New manufacturing process every
New manufacturing process every
2
2
years:
years:
¾
¾Parallel efforts Parallel efforts -- 30 month development cycles 30 month development cycles
¾
¾Upfront ESH Goals for each technologyUpfront ESH Goals for each technology
¾
¾Cross organizational team own ESH goals and ESH Cross organizational team own ESH goals and ESH roadmap
roadmap
¾
¾ESH Goals comprehend ESH Goals comprehend ““Virtual FactoryVirtual Factory””
¾Generational Environmental Footprint flat or shrinks
Intel
Intel
“
“
Copy Exactly
Copy Exactly
”
”
transfer methodology
transfer methodology
¾Rapid RampsDFESH
DFESH
ESH integrated throughout the TD process:
¾Chemical Use Policy and Approval Process
¾Manufacturing Process development
¾Chemical & Equipment selection
¾Waste Management
¾Facility design
¾Ergonomics and Equipment Safety
¾Manufacturing equipment selection
Materials go through Material and Supply
Chain Risk Assessment & Mitigation process
Piloting programs with Suppliers around
August 21, 2003 J Harrison 23
Estimated 300mm Emissions & Water
Estimated 300mm Emissions & Water
Use Relative to 200mm
Use Relative to 200mm
300mm is more Environmentally Friendly
300mm is more Environmentally Friendly
100
55%
42%
48% 40%
80
Volatile Organic Compounds
Perfluorocarbons
Hazardous Air Pollutants
Ultra-pure water
Vendor supplied data
Source: Intel
20 40 60
% Reduction
Environmental Performance 2002
Environmental Performance 2002
Intel’s EHS Report: www.intel.com/go/ehs
>55% of Chemical Waste recycled worldwide
>65% of Solid Waste recycled worldwide
Fresh water usage 16 million gal./day worldwide
30% reduction in VOC emissions since
’
99 (218
tons worldwide)
Global warming emissions 1.03 MMTCE (includes
electricity usage)
August 21, 2003 J Harrison 25
ERC for EBSM support
ERC for EBSM support
Maintain scientific integrity of program
Maintain scientific integrity of program
Source of future Industry scientists &
Source of future Industry scientists &
leaders
leaders
Characterization method’s and model’s
Characterization method’s and model’s
Safe use practices & Lifecycle
Safe use practices & Lifecycle
understanding
understanding
Identify lower ESH footprint alternatives
Identify lower ESH footprint alternatives
Backup
August 21, 2003 J Harrison 27
Crafting Films with Atomic Layer Deposition
Crafting Films with Atomic Layer Deposition
Step 3
Step 4 Step 2
Step 1
A A
A A B B
A AB
B
ALD: Today’s nanotechnology for
self-assembly by atomic layer
ALD: Today’s nanotechnology for
ALD: Today’s nanotechnology for
self
self
-
-
assembly by atomic layer
assembly by atomic layer
x y
High K for Gate Dielectrics
High K for Gate Dielectrics
Silicon substrate
Silicon substrate
1.2nm SiO
1.2nm SiO22
Gate
Gate
Silicon substrate
Silicon substrate
Gate
Gate
3.0nm High
3.0nm High--kk
90nm process
Capacitance 1X
Leakage 1X
Experimental high-k
1.6X
August 21, 2003 J Harrison 29
Tri
Tri
-
-
Gate Transistor Structure
Gate Transistor Structure
Current
Lg
Source
Drain
Gate
Tox
SiO2
HSi
50nm Resist Lines With
50nm Resist Lines With
193nm Light
193nm Light
“
“best focusbest focus””
