Index of /intel-research/silicon

(1)

September 2003 September 2003 Carolyn Block, PhD Carolyn Block, PhD Senior Staff Engineer Senior Staff Engineer

Extending Moore’s Law

(2)

Agenda

y

y Historical motivations for scalingHistorical motivations for scaling

y

y Si Si Research at IntelResearch at Intel

–

– Logic Technology DevelopmentLogic Technology Development

–

– 90 nm Technology Results90 nm Technology Results

y

y Extending technology using Moore’s LawExtending technology using Moore’s Law

–

– Technical Criteria / Key ChallengesTechnical Criteria / Key Challenges

–

– Research Directions: high K, Research Directions: high K, trigatetrigate, , nanotubesnanotubes........

y

y What comes next?What comes next?

y

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Birth of Microelectronics: Moore’s Law

Log

2

of the number of

components per integrated function

2 4 7 9 13 1 3 5 6 8 10 11 12 14 15 16 0

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

Year

“Dr.Gordon E.Moore is one of the new breed of electronic engineers, “Reduced cost is one

Of the big attractions of Integrated electronics, and The cost advantage continues To increase as the technology Evolves toward the production

(4)

Moore’s Law continues to be the benchmark

1K 1K 4K 4K 64K 64K 256K 256K 1M1M

16M 16M 4M 4M 64M 64M 4004 4004 8080 8080 8086 8086 80286

80286 i386™i386™

i486™

i486™ PentiumPentium

®

Pentium Pentium®®_II_II

Pentium Pentium®® _III_III

256M

256M 512M512M

Pentium Pentium®®₄

Itanium Itanium™™

1G 1G 2G2G

4G 4G

128M 128M

MemoryMemory

S

S MicroprocessorMicroprocessor 1965 Actual Data 1965 Actual Data

1960

1960 19651965 19701970 19751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010

16K 16K 1975 Projection

1975 Projection

(5)

Effects of Scaling

0.1 0.1 1 1 10 10 100 100 1,000 1,000 10,000 10,000 1970

1970 19801980 19901990 20002000 20102010

Pentium® 4 Processor Pentium® 4 Processor

Pentium® Pentium® 386 386 286 286 8080 8080 4004 4004

Clock Frequency (MHz)

0.001 0.01 0.1 1 10 100 1000

70 80 90 2000

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Effects of Scaling: Cost

0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

$

(7)

The beauty of silicon

1 GB 1 GB 64 MB 64 MB 4 MB 4 MB DRAMs DRAMs 12” 12” 8” 8” 6” 6” Wafer diameter Wafer diameter 0.15

0.15 µµmm 0.35

0.35 µµmm 0.8

0.8 µµmm

Feature size Feature size 2000 2000 1995 1995 1990 1990 1. Scaling device

dimensions downward

2. Scaling wafer diameter

(8)

The ingredients of scaling

Material Evolution in MOS

Material Evolution in MOS

2000’s 60’s 70’s 80’s 90’s Al SiO2 Al-Si SiO2 Poly Al-Cu SiO2 WSi2/Poly Ti/TiN Al-Cu SiO2 TiSi2/Poly

Ti/TiN

W

Al-Cu

SiO2 TiSi2/Poly

Ti/TiN

W

Low K

Al-Cu

SiO2/SiN

CSi2/Poly

Ti/TiN

W

ELK Cu

Silicon Silicon Silicon Silicon Silicon Silicon

New materials

Improved processing

New geometries

Scaling Will continue as long as

(9)

Agenda

y

–

y

–

y

(10)

Silicon Research at Intel

y

Logic Technology Development ( OR, CA, AZ)

–

– Lithography, Lithography, TransistorsTransistors, , InterconnectsInterconnects, Packaging, , Packaging, Environmentally Benign Materials

Environmentally Benign Materials

y

Non

-

Volatile Memory

–

– Ovonics (CA)Ovonics (CA)

–

– Polymers (OR)Polymers (OR)

y

Opto

-

electronics (CA)

y

MEMS ( CA)

y

(11)

Ronler Acres

F20: 200mm

130 nm Production

D1C: 300mm, 130nm Production 90nm Development

RP1: 300mm

Research D1D: 300mm

65 nm Development

(12)

Intel in Production with

Nanotechnology (< 100nm)

10000 10000 1000 1000 100 100 10 10 10 10 1 1 0.1 0.1 0.01 0.01 Micron

Micron NanoNano_meter_meter-

-1970 1980 1990 2000 2010 2020

1970 1980 1990 2000 2010 2020

Nominal feature size

(13)

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90 nm Generation Transistor

50nm

Silicide Layer

Silicon Gate Electrode

1.2 nm SiO₂ Gate Oxide

Strained Silicon

50 nm L_GATE + 1.2 nm Oxide + Strained Silicon for industry leading transistor performance

Future

Options

gate loop

engineering

New

transistor

structure

structure

Source: Intel

(15)

Interconnect Challenges: Delay

0 5 10 15 20 25 30 35 40 45

Delay i

n

ps

Gate Delay

Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low K

Interconnect Delay, Al & SiO2

Interconnect Delay, Cu & Low K

Gate w Cu

& Low K

•Interconnect Will Dominate Timing

Gate w Al & SiO2

(16)

90nm Interconnects

C

R

etch stop thin barriers

low K dielectrics

(17)

Agenda

y

–

y

–

y

(18)

How do we continue to drive

Moore’s Law?

y

CMOS scaling will continue for > 10 years

–

– Si Si CMOS + New Materials CMOS + New Materials

–

– Dielectrics and GateDielectrics and Gate

–

– Interconnect Interconnect

–

– ChannelChannel

y

Nanoscience

research is needed to facilitate

radical new scalable technologies in the future

–

– Need to identify most promising options (materials, Need to identify most promising options (materials, processes, structures)

processes, structures)

–

(19)

Technical criteria

y

CMOS compatibility

y

Energy efficiency

y

y ScalabilityScalability

y

y PerformancePerformance

y

y Architectural compatibilityArchitectural compatibility

y

y Sensitivity to parametric variationSensitivity to parametric variation

y

y Room temperature operationRoom temperature operation

y

(20)

MEMS for RF

MEMS for RF

Adaptable and Versatile

Silicon Technology

Silicon

Technology

Base

Nanotube/Nanowire

Nanotube/Nanowire

Transistors

Ovonics Memory

(21)

Key Challenges to Scaling

y

Transistor

–

– Gate Oxide LeakageGate Oxide Leakage

–

– SourceSource--drain leakagedrain leakage

–

– Short Channel PerformanceShort Channel Performance

–

– Vcc Vcc scalingscaling

y

Patterning

y

Interconnects, Packaging

–

(22)

Intel Nano Transistors

30nm Prototype1

20nm Prototype2

25 nm 15nm

15nm Prototype 15nm Prototype33

50nm Length (IEDM2002)

65nm Node 2005

45nm Node 2007

90nm Node 2003

32nm Node 2009

22nm Node 2011

10nm Prototype 10nm Prototype44

References

1. IEDM, R.

1. IEDM, R. ChauChauet al., 12/00et al., 12/00 2. 2001 Silicon

2. 2001 Silicon NanoelectronicsNanoelectronicsWorkshop, R.Workshop, R.ChauChauet al., 6/01et al., 6/01 3.

3.TeraHertzTeraHertzTransistor press briefing, G.Transistor press briefing, G.MarcykMarcyk& R.& R.ChauChau, 11/01, 11/01 4. 61st Device Research Conference, R.

(23)

Nanotechnology for Gate

Dielectrics

Silicon substrate

Silicon substrate

Gate

3.0nm High

3.0nm High--kk

Source: Intel

90nm process

90nm process Experimental highExperimental high--kk Silicon substrate

Silicon substrate

1.2nm SiO

1.2nm SiO₂₂

Gate

(24)

Experimental Tri

-

Gate

Transistor

Source

Source

Drain

Gate

y

Improved version of TeraHertz transistor

–

– Better performanceBetter performance

–

– Scalable to smaller sizes (low leakage)Scalable to smaller sizes (low leakage)

–

– Possible intercept towards end of decade?Possible intercept towards end of decade?

Source: Intel

Gate

Silicon

Silicon

Drain

Source

(25)

Future Nanotechnology will compliment

& extend Silicon Technology

*Source: Holmes et al, University

College Cork

Silicon

Silicon

Nanowire*

Nanotube/Nanowire

Carbon

(26)

CNT

-

FET Device Structure

1.4 nm diameter single wall CNT Mo S/D E-beam Ti/Au gate

8 nm ZrO2

(27)

Crossed Nanowire Structures: A

Powerful Strategy for Creation &

Integration of Nanodevices

Nanowires serve dual purpose: both active devices and

interconnects.

All key nanoscale metrics are defined during synthesis and

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Crossed Nanowire FETs

In crossed nanowire FETs (cNW-FET), all critical nanoscale metrics

are defined by synthesis and assembly:

• channel width by the active nanowire diameter (to 2 nm)

• channel length by the gate nanowire diameter (to 1-2 nm)

• gate dielectric oxide coating on the nanowires (to 1 atomic layer)

The conductance of cNW-FETs can be changed by more than 105-times

with less than 0.1 V variation in the nano-gate.

400 200 0 -200 -400 C u rrent (nA )

-1.0 -0.5 0.0 0.5 1.0

Bias (V)

S D

G

V_g(V):

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Device Demonstrated

(30)

Agenda

y

–

y

–

y

(31)

Future of

Nanocomputing

Silicon highway

Scalable new technology

limits

(32)

Nanotech Building Blocks

Sub 100nm particles

c. Molecular Assembly (directed and self assembly)

Macromolecules

Sub 100nm structures

Sub 100nm structures 10nm

(33)

Some alternative logic devices

Fas

ter Smal

ler

(34)

Conclusions

y

Intel’s sub

-

100nm technology is already a

production reality and continues to follow

Moore’s Law

y

We believe the Silicon nanotechnology is

extendable for at least 10 years

y

Nanoscience

research is needed to facilitate

radical new scalable technologies for the future

–

we are open

-

minded about future options and

collaborations between industries, universities

and governments is essential

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For further information on Intel's silicon technology, please visit the Silicon Showcase at